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Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics with Bit Reduction Technique
(Articles)
S. K. Manikandan
,
C. Palanisamy
Circuits and Systems
Vol.7 No.9
，July 27, 2016
DOI:
10.4236/cs.2016.79224
2,216
Downloads
4,992
Views
Citations
Implementation of
N
-Bit Binary Multiplication Using
N
- 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method
(Articles)
M. Nisha Angeline
,
S. Valarmathy
Circuits and Systems
Vol.7 No.9
，July 19, 2016
DOI:
10.4236/cs.2016.79203
1,779
Downloads
3,054
Views
Citations
High Performance Novel Square Root Architecture Using Ancient Indian Mathematics for High Speed Signal Processing
(Articles)
Arindam Banerjee
,
Aniruddha Ghosh
,
Mainuck Das
Advances in Pure Mathematics
Vol.5 No.8
，June 11, 2015
DOI:
10.4236/apm.2015.58042
3,332
Downloads
5,040
Views
Citations
This article belongs to the Special Issue on
Iterative Methods
A Thematic Analysis on Vedic Mathematics and Its Importance
(Articles)
Sher Singh Raikhola
,
Dinesh Panthi
,
Eka Ratna Acharya
,
Kanhaiya Jha
Open Access Library Journal
Vol.7 No.8
，August 28, 2020
DOI:
10.4236/oalib.1106665
1,386
Downloads
6,951
Views
Citations
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