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S. Mahapatra, V. Vaish, C. Wasshuber, K. Banerjee and A. M. Ionescu, “Analytical Modeling of Single Electron Transistor for Hybrid CMOS-SET Analog IC Design,” IEEE Transactions on Electron Devices, Vol. 51, No. 11, 2004, pp. 1772-1782. Hdoi:10.1109/TED.2004.837369

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