Farjad-Rad, R., Dally, W., Ng, H.-T., Senthinathan, R., Lee, M.-J.E., Rathi, R. and Poulton, J. (2002) A Low-Power Multiplying DLL for Low-Jitter Multigigaherz Clock Generation. IEEE Journal of Solid State Circuit, 37, 1804-1811.
http://dx.doi.org/10.1109/JSSC.2002.804340

has been cited by the following article:

• TITLE: A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop

  AUTHORS: Xinjie Wang, Tadeusz Kwasniewski

  KEYWORDS: Static Phase Offset, Multiplying Delay-Locked Loop, Deterministic Jitter, Reference Spur, PLL

  JOURNAL NAME: Circuits and Systems, Vol.6 No.1, January 21, 2015

  ABSTRACT: Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.