Stability and Leakage Analysis of a Novel PP Based 9T SRAM Cell Using N Curve at Deep Submicron Technology for Multimedia Applications
Shilpi Birla, Rakesh Kumar Singh, Manisha Pattanaik
DOI: 10.4236/cs.2011.24038   PDF    HTML     6,878 Downloads   11,356 Views   Citations


Due to continuous scaling of CMOS, stability is a prime concerned for CMOS SRAM memory cells. As scaling will increase the packing density but at the same time it is affecting the stability which leads to write failures and read disturbs of the conventional 6T SRAM cell. To increase the stability of the cell various SRAM cell topologies has been introduced, 8T SRAM is one of them but it has its limitation like read disturbance. In this paper we have analyzed a novel PP based 9T SRAM at 45 nm technology. Cell which has 33% increased SVNM (Static Voltage Noise Margin) from 6T and also 22%.reduced leakage power. N curve analysis has been done to find the various stability factors. As compared to the 10T SRAM cell it is more area efficient.

Share and Cite:

S. Birla, R. Singh and M. Pattanaik, "Stability and Leakage Analysis of a Novel PP Based 9T SRAM Cell Using N Curve at Deep Submicron Technology for Multimedia Applications," Circuits and Systems, Vol. 2 No. 4, 2011, pp. 274-280. doi: 10.4236/cs.2011.24038.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] M. Sinangil, V. Naveen and A. P. Chandrakasan, “A Reconfi-gurable 8T Ultra–Dynamic Voltage Scalable (U-DVS) SRAM in 65nm CMOS,” IEEE Journal Solid-State of Circuits, Vol. 44, No. 11, 2009, pp. 3163-3173. doi:10.1109/JSSC.2009.2032493
[2] R. E. Aly and M. A. Bayoumi, “Low-Power Cache Design Using 7T SRAM Cell,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 54, No. 4, 2007, pp. 318-322. doi:10.1109/TCSII.2006.877276
[3] Z. Liu and V. Kursun, “Characterization of a Novel Nine-Transistor SRAM Cell,” IEEE Transaction of Very large Scale Integration Systems, Vol. 16, No. 4, 2008, pp. 488-492.
[4] B. H. Calhoun and A. P. Chandrakasan “Static Noise Margin Variation for Sub-threshold SRAM in 65 nm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 7, 2006, pp. 1673-1679. doi:10.1109/JSSC.2006.873215
[5] Y. Chung and S.-H. Song, “Implementation of Low-Voltage Static RAM with Enhanced Data Stability and Circuit Speed,” Microelectronics Journal, Vol. 40, No. 6, 2009, pp. 944-951. doi:10.1016/j.mejo.2008.11.063
[6] E. Seevinck, et al., “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-State Circuits, Vol. 22, No. 5, 1987, pp. 748-754. doi:10.1109/JSSC.1987.1052809
[7] C. Wann, et al., “SRAM Cell Design for Stability Methodology,” 2005 IEEE VLSI-TSA International Symposium on VLSI Technology, 25-27 April 2005, pp. 21-22.
[8] E. Grossar, M. Stucchi and K. Maex, “Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 11, 2006, pp. 2577-2588. doi:10.1109/JSSC.2006.883344
[9] S. Birla, M. Pattanaik and R. K. Singh, “Static Noise Margin Analysis of Various SRAM Topologies,” IACSIT International Journal of Engineering and Technology, Vol. 3, No. 3, 2011, pp. 304-309.
[10] S. Birla, N. Kr. Shukla, M. Pattanaik and R. K. Singh, “Device and Circuit Design Challenges for Low Leakage SRAM for Ultra Low Power Applications,” Canadian Journal on Electrical & Electronics Engineering, Vol. 1, No. 7, 2010, pp. 157-167.

Copyright © 2024 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.