Timing-Driven Variation-Aware Partitioning and Optimization of Mixed Static-Dynamic CMOS Circuits

Kumar Yelamarthi

School of Engineering and Technology, Central Michigan University, Mt Pleasant, USA.

DOI: 10.4236/cs.2013.42027                

Abstract

The advancement in CMOS technology has surpassed the progress in computer aided design tools, creating an avenue for new design optimization flows. This paper presents a design level transistor sizing based timing optimization algorithms for mixed-static-dynamic CMOS logic designs. This optimization algorithm performs timing optimization through partitioning a design into static and dynamic circuits based on timing critical paths, and is further extended through a process variation aware circuit level timing optimization algorithm for dynamic CMOS circuits. Implemented on a 64-b adder and ISCAS benchmark circuits for mixed-static-dynamic CMOS, the design level optimization algorithm demonstrated a critical path delay improvement of over 52% in comparison with static CMOS implementation by state-of-the-art commercial optimization tools.

Keywords

Timing Optimization; Dynamic CMOS Circuits; Process Variations; Delay Uncertainty

Conflicts of Interest

The authors declare no conflicts of interest.

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