Article citationsMore>>
V. Sundararajan, S. S. Sapatnekar and K. K. Parhi, “Fast and Exact Transistor Sizing Based on Iterative Relaxation,” IEEE Transactions on CAD, Vol. 21, No. 5, 2002, pp. 568-581.
has been cited by the following article:
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TITLE:
Timing-Driven Variation-Aware Partitioning and Optimization of Mixed Static-Dynamic CMOS Circuits
AUTHORS:
Kumar Yelamarthi
KEYWORDS:
Timing Optimization; Dynamic CMOS Circuits; Process Variations; Delay Uncertainty
JOURNAL NAME:
Circuits and Systems,
Vol.4 No.2,
April
17,
2013
ABSTRACT:
The advancement in CMOS technology has surpassed the progress in computer aided design tools, creating an avenue for new design optimization flows. This paper presents a design level transistor sizing based timing optimization algorithms for mixed-static-dynamic CMOS logic designs. This optimization algorithm performs timing optimization through partitioning a design into static and dynamic circuits based on timing critical paths, and is further extended through a process variation aware circuit level timing optimization algorithm for dynamic CMOS circuits. Implemented on a 64-b adder and ISCAS benchmark circuits for mixed-static-dynamic CMOS, the design level optimization algorithm demonstrated a critical path delay improvement of over 52% in comparison with static CMOS implementation by state-of-the-art commercial optimization tools.