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https://doi.org/10.1063/1.1713035

has been cited by the following article:

• TITLE: Influence of Temperature and Pentacene Thickness on the Electrical Parameters in Top Gate Organic Thin Film Transistor

  AUTHORS: Abdoul Kadri Diallo, El Hadji Babacar Ly, Diène Ndiaye, Diouma Kobor, Marcel Pasquinelli, Abdou Karim Diallo

  KEYWORDS: Pentacene, Organic Transistor, Top Gate, Thin Film Transistor, Bias Stress, Parylene

  JOURNAL NAME: Advances in Materials Physics and Chemistry, Vol.7 No.3, March 27, 2017

  ABSTRACT: In this contribution, we report on the effect of pentacene thickness and temperature on the performance of top gate transistors. We first investigated the temperature dependence of the transport properties in the temperature range of 258 K - 353 K. The electrical characteristics showed that the threshold voltage (VT) and the onset voltage (Von) remain unchanged. However, the subthreshold current (Ioff), the on-current (Ion) and the field effect mobility (μ) are highly affected with a slight deterioration of subthreshold slope. We observed Arrhenius-like behavior suggesting a thermally activated mobility with an activation energy EA = 68 meV. Moreover the dependence of the charge carrier mobility on the organic semiconductor thickness has also been studied. The mobility decreased as the pentacene thickness increases whereas the threshold voltage and Ioff current remain minimally affected. In order to understand the transport properties and in view to put in light morphology peculiarities of pentacene, AFM images were performed. It turns out that the pentacene grain sizes are smaller and disorganized as the film thickness increases, and charge carriers are more prone to be trapped, leading to decrease the field effect mobility and the Ion current. The devices were also tested under bias stress and the transistors with low thicknesses exhibited a relatively good electrical stability compared to those with high pentacene thicknesses. This work points out the influence of temperature, semiconductor thickness and bias stress effect on the device performance and stability of transistor using top gate configuration.