Y. L. Tsang, S. Chattopadhyay, S. Uppal, E. Escobedo-Cousin, H. Ramakrishnan, S. H. Olsen and A. G. O’Neill, “Modeling of the Threshold Voltage in Strained Si/Si1 ? xGex/Si1 ? yGey(x ≥ y) CMOS Architectures,” IEEE Transac-tions on Electron Devices, Vol. 54, No. 11, November 2007, pp. 3040-3048.

has been cited by the following article:

• TITLE: An Explicit Surface-Potential Based Biaxial Strained-Si n-MOSFET Model for Circuit Simulation

  AUTHORS: Tapas K. Maiti, Animesh Banerjee, Chinmay K. Maiti

  KEYWORDS: Strained-Si, Heterostructure, 2-DEG, Surface Potential, Regional Approach

  JOURNAL NAME: Engineering, Vol.2 No.11, November 26, 2010

  ABSTRACT: In this paper, a charge sheet surface potential based model for strained-Si nMOSFETs is presented and validated with numerical simulation. The model considers sub band splitting in the 2-DEG at the top heterointerface in SiGe layer and also the dependence of electron concentration at heterointerface with the gate oxide. The model is scalable with strained-Si material parameters with physically derived flat-band voltages. An explicit relation for surface potential as a function of terminal voltages is developed. The model is derived from regional charge-based approach, where regional solutions are physically derived. The model gives an accurate description of drain current both in the weak and strong inversion regions of operation. The results obtained from the model developed are benchmarked with commercial numerical device simulator and is found to be in excellent agreement.