M. Yamaoka, N. Maeda, Y. Shinozaki, K. Nii, S. Shimada, K. Yanagi-sawa and T. Kawahara, “90-nm Process-Variation Adaptive Embedded SRAM Modules with Power-Line-Floating Write Technique,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 3, 2006, pp. 705-711. doi:10.1109/JSSC.2006.869786

has been cited by the following article:

• TITLE: Fast CR-SRAM Using New Charge-Recycling Scheme

  AUTHORS: Leilei Li, Xin Chen, Xu Wang

  KEYWORDS: SRAM; Lower-Power; Charge-Recycling

  JOURNAL NAME: Engineering, Vol.4 No.8, August 31, 2012

  ABSTRACT: In this paper, a CR-SRAM using new charge recycling scheme is described, novel bit-line pre-charge voltage distribution is proposed. The SRAM pre-charge voltage level is designed by logarithm instead of linear. The new design leads to improvement in speed compared to the original CR-SRAM. Simulation results show that the new CR-SRAM using novel pre-charge voltage distribution scheme reduced the write access time by 34% with 9% power dissipation penalty.