O. Hirabayashi, A. Kawasumi, A. Suzuki, Y. Takeyama, K. Kushida, T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, T. Nakazato, Y. Shizuki, N. Kushiyama and T. Yabe, “A Process-Variation-Tolerant Dual-Power-Supply SRAM with 0.179 um2 Cell in 40 nm CMOS Using Level Programmable Wordline Driver,” ISSCC Digg Technology Papers, 2009, pp. 458-459.

has been cited by the following article:

• TITLE: Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration

  AUTHORS: Hiroshi Makino, Naoya Okada, Tetsuya Matsumura, Koji Nii, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda

  KEYWORDS: Static Random Access Memory (SRAM); Write Noise Margin (WNM); Vth Fluctuation; Variance; WNM Distribution

  JOURNAL NAME: Circuits and Systems, Vol.3 No.3, June 25, 2012

  ABSTRACT: An accelerated evaluation method for the SRAM cell write margin is proposed using the conventional Write Noise Margin (WNM) definition based on the “butterfly curve”. The WNM is measured under a lower word line voltage than the power supply voltage VDD. A lower word line voltage is chosen in order to make the access transistor operate in the saturation mode over a wide range of threshold voltage variation. The final WNM at the VDD word line voltage, the Accelerated Write Noise Margin (AWNM), is obtained by shifting the measured WNM at the lower word line voltage. The WNM shift amount is determined from the measured WNM dependence on the word line voltage. As a result, the cumulative frequency of the AWNM displays a normal distribution. Together with the maximum likelihood method, a normal distribution of the AWNM drastically improves development efficiency because the write failure probability can be estimated from a small number of samples. The effectiveness of the proposed method is verified using the Monte Carlo simulation.