H. Loukil, A. Ben Atitallah and N. Masmoudi, “An Efficient FPGA Parallel Architecture for H.264/AVC Intra Prediction Algorithm,” Proceeding of International Conference on Embedded Systems and Critical Applications, Gammarth, Tunisia, 2008, pp. 191196.

has been cited by the following article:

• TITLE: FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder

  AUTHORS: Hassen Loukil, Imen Werda, Nouri Masmoudi, Ahmed Ben Atitallah, Patrice Kadionik

  KEYWORDS: Nios H.264, FPGA, Intra 16 × 16, NIOS-II, SOPC Design

  JOURNAL NAME: Circuits and Systems, Vol.1 No.1, July 28, 2010

  ABSTRACT: In this paper, we propose novel hardware architecture for intra 16 × 16 module for the macroblock engine of a new video coding standard H.264. To reduce the cycle of intra prediction 16 × 16, transform/quantization, and inverse quantization/inverse transform of H.264, an advanced method for different operation is proposed. This architecture can process one macroblock in 208 cycles for all cases of macroblock type by processing 4 × 4 Hadamard transform and quantization during 16 × 16 prediction. This module was designed using VHDL Hardware Description Language (HDL) and works with a 160 MHz frequency using ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA. The system also includes software running on an NIOS-II processor in order to implementing the pre-processing and the post-processing functions. Finally, the execution time of our HW solution is decreased by 26% when compared with the previous work.