R. Salami, C. Laflamme, J-P. Adoul and A. Kataoka, “Design and Description of CS-ACELP A Toll Quality 8 Kb/s Speech Coder,” IEEE Transactions on Speech and Audio Processing, Vol. 6, No. 2, 1998, pp. 116-130.doi10.1109/89.661471 - References

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R. Salami, C. Laflamme, J-P. Adoul and A. Kataoka, “Design and Description of CS-ACELP: A Toll Quality 8 Kb/s Speech Coder,” IEEE Transactions on Speech and Audio Processing, Vol. 6, No. 2, 1998, pp. 116-130. doi:10.1109/89.661471

has been cited by the following article:

TITLE: Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications

AUTHORS: Mohamed Atri, Fatma Sayadi, Wajdi Elhamzi, Rached Tourki

KEYWORDS: Linear Predictive Coding; System on Programmable Chip; FPGA; Co-Design

JOURNAL NAME: Journal of Signal and Information Processing, Vol.3 No.1, February 29, 2012

ABSTRACT: The LPC “Linear Predictive Coding” algorithm is a widely used technique for voice coder. In this paper we present different implementations of the LPC algorithm used in the majority of voice decoding standard. The windowing/autocorrelation bloc is implemented by three different versions on an FPGA Spartan 3. Allowing the possibility to integrate a Microblaze processor core a first solution consists of a pure software implementation of the LPC using this core RISC processor. Second solution is a pure hardware architecture implemented using VHDL based methodology starting from description until integration. Finally, the autocorrelation core is then proposed to be implemented using hardware/software (HW/SW) architecture with the existing processor. Each architecture performances are compared for different data lengths.