J. Lin and B. Haroun, “An Embedded 0.8V/480μW 6b/22MHz Flash ADC in 0.13 μm Digital CMOS Process Using Nonlinear Double-Interpolation Technique,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 12, 2002, pp. 1610-1617. doi:10.1109/JSSC.2002.804333

has been cited by the following article:

• TITLE: Novel Threshold-Based Standard-Cell Flash ADC

  AUTHORS: Marcel Siadjine Njinowa, Hung Tien Bui, François-Raymond Boyer

  KEYWORDS: Flash ADC; Standard Cells; Data Converters

  JOURNAL NAME: Circuits and Systems, Vol.3 No.1, December 31, 2011

  ABSTRACT: This paper introduces a novel standard-cell flash architecture for implementing analog-to-digital converters (ADC). The proposed ADC consists of several CMOS inverters all having their inputs connected to a common input node. The out-put of the ADC is a thermometer code generated by the inverter outputs. Depending on the relationship between the input signal and a given inverter’s threshold voltage, the output will either be ‘0’ or ‘1’. By having many inverters with different threshold voltages, it is possible to create a 3-bit flash ADC. Even though the system is inherently non-linear, mathematical optimization has been done in order to improve its linearity. The proposed circuit dissipates 6.7 mW and uses in total 672 transistors of PMOS and NMOS types. This ADC is designed and simulated using TSMC’s 0.18 μm CMOS and results show that the proposed circuit works as expected even in presence of process variations.