Abdelhadi, A.M.S. and Li, H. (2021) Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs. International Conference on Field-Programmable Logic and Applications, 43, 312-318.
https://doi.org/10.1109/FPL53798.2021.00062

has been cited by the following article:

• TITLE: Review on the Usage of Synchronous and Asynchronous FIFOs in Digital Systems Design

  AUTHORS: Dongwei Hu, Yuejun Lei, Linan Wang

  KEYWORDS: First-Input-First-Output, System-on-Chip, Network-on-Chip, Advanced eXtensible Interface, Asynchronous

  JOURNAL NAME: Engineering, Vol.16 No.3, March 29, 2024

  ABSTRACT: First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implemented in different ways. FIFOs are used not only for the pipeline design within a processor, for the inter-processor communication networks, for example Network-on-Chips (NoCs), but also for the peripherals and the clock domain crossing at the whole SoC level. In this paper, we review the interface, the circuit implementation, and the various usages of FIFOs in various levels of the digital design. We can find that the usage of FIFOs could greatly facilitate the signal storage, signal decoupling, signal transfer, power domain separation and power domain crossing in digital systems. We hope that more attentions are paid to the usages of synchronous and asynchronous FIFOs and more sophististicated usages are discovered by the digital design communities.