TITLE:
Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation
AUTHORS:
Agord de Matos Pinto Jr, Raphael Ronald Noal Souza, Mateus Biancarde Castro, Eduardo Rodrigues de Lima, Leandro Tiago Manêra
KEYWORDS:
Phase Locked Loop (PLL), Voltage-Controlled Ring Oscillators (VCRO), Dual-Delay-Path DDP, Delay Cells
JOURNAL NAME:
Circuits and Systems,
Vol.14 No.6,
June
30,
2023
ABSTRACT: This work summarizes the structure and
operating features of a high-performance 3-stage dual-delay-path (DDP)
voltage-controlled ring oscillator (VCRO) with self-biased delay cells for
Phase-Locked Loop (PLL) structurebased clock generation and digital system
driving. For a voltage supply VDD = 1.8 V, the resulting set of performance
parameters include power consumption PDC = 4.68 mW and phase noise PN@1MHz =
-107.8 dBc/Hz. From the trade-off involving PDC and PN, a system level high
performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC
L180), the proposed VCRO was designed at Cadence environment and optimized at
MunEDA WiCkeD tool.