Kiran, K.R., Kumar, C.A. and Suresh Kumar, M. (2015) Design and Analysis of a Novel High-Speed Adder Based Hardware Efficient Discrete Cosine Transform (DCT). 2015 5th International Conference on Advances in Computing and Communications (ICACC), Kochi, 2-4 September 2015, 169-173.
https://doi.org/10.1109/ICACC.2015.88

has been cited by the following article:

• TITLE: A Low-Area, Low-Power Dynamically Reconfigurable 64-Bit Media Signal Processing Adder

  AUTHORS: Priscilla Sharon Allwin, Chien-In Henry Chen

  KEYWORDS: Media Signal Processing (MSP), Reconfigurable Adder, Dynamic Reconfiguration

  JOURNAL NAME: Journal of Computer and Communications, Vol.9 No.3, March 22, 2021

  ABSTRACT: Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video signal and image processing. In this paper, a novel low-area, energy-efficient 64-bit dynamically reconfigurable adder is presented. This adder can be run-time configured to different reconfigurable word lengths based on the partition signal commands provided. Moreover, the design is partitioned into sub-blocks based on functionality to save power, i.e., configuring the computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. Only functions that are needed are powered on, and the rest of the functionality is powered off. The proposed 64-bit dynamically reconfigurable media signal processing (MSP) adder is implemented in the 180 nm CMOS technology at 1.8 V, requiring an area of 39,478 μm2 and a power of 79.24 mW. The dynamic MSP adder achieves a 15.7% reduction in area and a 59.2% reduction in power than the 64-bit MSP adder.