Troutman, R.R. (1979) VLSI Limitation from Drain-Induced Barrier Lowering. IEEE Transactions on Electron Devices, 26, 461-469.
https://doi.org/10.1109/T-ED.1979.19449

has been cited by the following article:

• TITLE: 28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part I

  AUTHORS: Ali Mohsen, Adnan Harb, Nathalie Deltimple, Abraham Serhane

  KEYWORDS: UTBB FD-SOI: Ultra-Thin Body and Box Fully Depleted Silicon on Insulator, Tri-Gate FinFET, DIBL: Drain Induced Barrier Lowering

  JOURNAL NAME: Circuits and Systems, Vol.8 No.4, April 30, 2017

  ABSTRACT: Nowadays, transistor technology is going toward the fully depleted architecture; the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications.