Vangal, S.R., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Singh, A., Jacob, T., Jain, S., et al. (2008) An 80-Tile Sub-100-w Teraflops Processor in 65-nm cmos. IEEE Journal of Solid-State Circuits, 43, 29-41.

has been cited by the following article:

• TITLE: Twist-Routing Algorithm for Faulty Network-on-Chips

  AUTHORS: Kunwei Zhang, Thomas Moscibroda

  KEYWORDS: Network-on-Chip (NoC), Fault-Tolerant Routing, Maze-Routing Algorithm, GOAFR+ Algorithm, Bounding Circle

  JOURNAL NAME: Journal of Computer and Communications, Vol.4 No.14, November 11, 2016

  ABSTRACT: This paper introduces Twist-routing, a new routing algorithm for faulty on-chip networks, which improves Maze-routing, a face-routing based algorithm which uses deflections in routing, and archives full fault coverage and fast packet delivery. To build Twist-routing algorithm, we use bounding circles, which borrows the idea from GOAFR+ routing algorithm for ad-hoc wireless networks. Unlike Maze-routing, whose path length is unbounded even when the optimal path length is fixed, in Twist-routing, the path length is bounded by the cube of the optimal path length. Our evaluations show that Twist-routing algorithm delivers packets up to 35% faster than Maze-routing with a uniform traffic and Erdos-Rényi failure model, when the failure rate and the injection rate vary.