Sarwar, S.S., Saqueb., S.A.N., Quaiyum, F. and Harun-Ur Rashid, A.B.M. (2013) Memristor-Based Nonvolatile Random Access Memory: Hybrid Architecture for Low Power Compact Memory Design. IEEE Access, 1, 29-34.
http://dx.doi.org/10.1109/ACCESS.2013.2259891

has been cited by the following article:

• TITLE: Design and Analysis of Low Power Hybrid Memristor-CMOS Based Distinct Binary Logic Nonvolatile SRAM Cell

  AUTHORS: Veerappan Saminathan, Kuppusamy Paramasivam

  KEYWORDS: Memristor-CMOS, Nonvolatile Memory, Power Consumption, DBL, PWL Input

  JOURNAL NAME: Circuits and Systems, Vol.7 No.3, March 30, 2016

  ABSTRACT: Memristor is a newly found fourth circuit element for the next generation emerging nonvolatile memory technology. In this paper, design of new type of nonvolatile static random access memory cell is proposed by using a combination of memristor and complemented metal oxide semiconductor. Biolek memristor model and CMOS 180 nm technology are used to form a single cell. By introducing distinct binary logic to avoid safety margin is left for each binary logic output and enables better read/write data integrity. The total power consumption reduces from 0.407 mw (milli-watt) to 0.127 mw which is less than existing memristor based memory cell of the same CMOS technology. Read and write time is also significantly reduced. However, write time is higher than conventional 6T SRAM cell and can be reduced by increasing motion of electron in the memristor. The change of the memristor state is shown by applying piecewise linear input voltage.