J. Figueras and A. Ferre, “Possibilities and Limitations of IDDQ Testing in Submicron CMOS,” IEEE Transaction Components, Packaging and Manufacturing Technology – Part B, Vol. 21, No. 4, November 1998, pp. 352-359.

has been cited by the following article:

• TITLE: ΔIDDQ Testing of a CMOS Digital-to-Analog Converter Considering Process Variation Effects

  AUTHORS: Rajiv Soundararajan, Ashok Srivastava, Siva Sankar Yellampalli

  KEYWORDS: IDDQ Testing, DAC, BICS, Sub-Micron CMOS IC, ΔIDDQ Testing, Process Variation, Background Current

  JOURNAL NAME: Circuits and Systems, Vol.2 No.3, July 6, 2011

  ABSTRACT: In this paper, we present the implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters. A 12-bit digital-to-analog converter (DAC) is designed as the circuit under test (CUT). The BICS uses frequency as the output for fault detection in CUT. A fault is detected if it causes the output frequency to deviate more than ±10% from the reference frequency. The output frequencies of the BICS for various (MOSIS) model parameters are simulated to check for the effect of process variation on the frequency deviation. A set of eight faults simulating manufacturing defects in CMOS data converters are injected using fault-injection transistors and tested successfully.