J. Gonzalez and E. Alarcon, “Clock-Jitter Induced Distortion in High-Speed CMOS Switched-Current Segmented Digital to Analog Converters,” International Symposium on Circuits and Systems (ISCAS’01), Sydney, 6-9 May 2001, pp. 1512-1515.

has been cited by the following article:

• TITLE: A 12-Bit 1-Gsample/s Nyquist Current-Steering DAC in 0.35 µm CMOS for Wireless Transmitter

  AUTHORS: Peiman Aliparast, Hossein B. Bahar, Ziaadin D. Koozehkanani, Jafar Sobhi, Gader Karimian

  KEYWORDS: Wireless Transmitter, 3-D Thermometer Decoding, Current Steering DAC, WLAN, Integrated Circuits, CMOS

  JOURNAL NAME: Circuits and Systems, Vol.2 No.2, March 28, 2011

  ABSTRACT: The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for the proposed DAC leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3-D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1-GSample/s frequency. Simulation results show that the spurious- free-dynamic-range (SFDR) in Nyquist rate is better than 64 dB for sampling frequency up to 1-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. The chip has been processed in a standard 0.35 µm CMOS technology. Active area of chip is 1.37 mm2.