Hsu, C.W., Karthik, T., Yu, S.A. and Peter, R.K. (2011) A 2.2 GHz PLL Using a Phase-Frequency Detector with an Auxiliary Sub-Sampling Phase Detector for in-Band Noise Suppression. Proceedings of IEEE Custom Integrated Circuits Conference, San Jose, 19-21 September 2011, 1-4.

has been cited by the following article:

• TITLE: A Modified PFD Based PLL with Frequency Dividers in 0.18-µm CMOS Technology

  AUTHORS: N. K. Anushkannan, H. Mangalam

  KEYWORDS: PFD, Dead Zone, VCO, Power, PLL

  JOURNAL NAME: Circuits and Systems, Vol.7 No.13, November 18, 2016

  ABSTRACT: This paper introduces a modified design of CMOS dynamic Phase Frequency Detector (PFD). The proposed PFD circuit (PPFD) is designed, simulated and the results obtained are analyzed. In order to reduce dead zone, internal signal routing is used in the PPFD circuit. To extend, Phase Locked Loop (PLL) is designed and it is verified with two different Frequency Divider (FD) circuits. There is a decrease in area of the PPFD circuit with 16 transistors and dissipates power of 40.8 pW for 1.2 V power supply. The pre-layout simulation result shows that the PPFD circuit has an elimination of a dead zone. Further, it works with the high speed and reduced power operated in the reference frequency of 50 MHz and the feedback frequency up to 4 GHz.