A High Power-Added-Efficiency 2.5-GHz Class-F Power Amplifier Using 0.5 μm GaN on SiC HEMT Technology


This paper proposed the high-frequency, multi-harmonic-controlled, Class-F power amplifier (PA) implemented with 0.5 μm GaN Hetrojunction Electron Mobility Transistor (HEMT). For PA design at high frequencies, parasitics of a transistor significantly increase the difficulty of harmonic manipulation, compared to low-frequency cases. To overcome this issue, we propose a novel design methodology based on a band-reject, low-pass, output matching network, which is realized with passive components. This network provides optimal fundamental impedance and allows harmonic control up to the third order to enable an efficient Class-F behavior. The implemented PA exhibits performance at 2.5 GHz with a 50% PAE, 14 dB gain, and 10 W output power.

Share and Cite:

Lin, C. , Chiu, H. , Chou, M. , Wang, H. and Huang, M. (2016) A High Power-Added-Efficiency 2.5-GHz Class-F Power Amplifier Using 0.5 μm GaN on SiC HEMT Technology. Journal of Computer and Communications, 4, 74-78. doi: 10.4236/jcc.2016.43011.

1. Introduction

In modern wireless communication systems, RF power amplifiers (PAs) are one of the most important part of the transmitters. Increasing the system efficiency, it is necessary that the PA is highly efficient as it is the most power hungry device. High efficiency of a PA means low power consumption, less cooling requirement, which reduce the overall cost of the RF front-ends as well. The original and novel design methodology schematic of class-F power amplifier is shown in Figure 1 and Figure 2. When the waveform of Vmax is too large, it may cause electric crystal burned limit, greatly reduces our ideas to make the design of the circuit. In order to improve this situation, we made the reinforcement foe class-F power amplifier circuit especially. At the output port, a λ/4 microstrip lines were used which operating frequency ω0 as Figure 1 shown. This schematic allows the odd-order harmonic signals are retained in the drain terminal, and even order harmonics signals were shorted to ground, and this design allows the drain terminal of the voltage waveform is adjusted to a square wave, avoid Vmax impact caused by too much.

Figure 1.Original design methodology schematic of class-F power amplifier.

Figure 2. Novel design methodology schematic of class-F power amplifier.

The principle of class-F power amplifier is retained by an infinite number of odd-order harmonics signal waveform reshape using to produce the desired square-wave to improve the drain terminal of the voltage waveform, that if you do not use the microstrip line to achieve this result, there are other ways to solve. Figure 2 shows an important answer, that is to use multiple sets of LC resonant circuit for the output matching network. Which can storage energy at fixed operating frequency, will affect the larger signal waveform reservations. As for the other less important signals are ignored on the power loss less area and the resonant circuit. For example, in Figure 2, this circuit only adds a LC resonant at 3ω0, and in Figure 3, though the wave drain terminal voltage waveform has a little difference compare to the ideal square wave, but in inhibition of drain terminal Vmax has significant performance. From this, when the odd harmonic signals richer, more connected composite waveform approximates a square wave, and the more conversion efficiency. In theory, more than the increase in the output of 5ω0 even 7ω0 resonant circuit, will contribute to better performance characteristics of the class-F power amplifier.

2. Circuit Design

The chip photograph is shown in Figure 4, only including input matching network where the passive components were arranged on the chip with dc and rf pads. And full schematic is shown in Figure 5. We used RC resonant to solving low frequency oscillation in rf input matching. The complete device small/large-signal modeling for HEMTs and passive components had been built for circuit simulation. The size of the chip is 1500 × 1000 μm2, and the gate width for M is 12 × 100 μm2. And the output matching network is on PCB with wire

Figure 3. Waveform of class-F power amplifier.

Figure 4. Chip photograph of the proposed PA.

Figure 5. Schematic of the class-F power amplifier.

bonding as Figure 6 shown. It presents that is used LC band-reject structure 3f0 and low-pass filter for f0, that in order to reducing the loss from the effect of dc load. In the measurement setup, a off-chip inductor to be rf choke was used through bonding wire at the output port.

3. Experiment Result

The dc biases for first-stage amplifier are VD = 28 V and VG = −2.5 V. Figure 7 shows the result measured and simulated small-signal return loss curves. The signal source for large-signal performance measurement was generated by Agilent E8257D Signal Generator. The output signal of the PA was measured by Agilent E4440A spectrum analyzer. We made S22 return loss at higher about 500 MHz than S11. Because when VD = 28 V and VG = −2.5 V, the transistor is on cutoff region. And when at the signal source for large-signal, the transistor will be into saturation. Then the output port will occur parasitics capacitance, it will make the return loss close to the lower frequency. Figure 8 shows the curves of output power, power gain and PAE as a function of the input power at the frequency of 2.5 GHz. The maximum output of 40 dBm with PAE of 62% can be achieved in simulation. And the measured output power was limited with lower PAE performance about 50%. Figure 9 exhibits the curves of saturated output power and gain versus frequency for measurement.

Figure 6. Output matching network of the class-F power amplifier.

Figure 7. Return loss of the proposed class-F power amplifier.

Figure 8. Large-signal performance of the proposed class-F power amplifier.

Figure 9. Saturation output power and gain as a function of frequency.

Table 1. Performance comparison of reported power amplifiers using a GAN device.

4. Conclusion

This paper proposed class-F power amplifier in 0.5 μm GaN HEMT process. The input matching was designed on-chip to reduce the PA module size. The measurement of power amplifier has a high power performance from 2.3 GHz to 2.7 GHz. The chip size is 1.5 × 1 mm2. The proposed power amplifier can be used for S-band communication system application. And the performance comparison is shown in Table 1.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] Chen, K. and Peroulis, D. (2013) A 3.1-GHz Class-F Power Amplifier With 82% Power-Added-Efficiency. IEEE Mi-crowave and Wireless Components Letters, 23, 436-438. http://dx.doi.org/10.1109/LMWC.2013.2271295
[2] Kalim, D., Pozdniakov, D. and Negra, R. (2012) A 3.37 GHz Class-F?1 Power Amplifier with 77% PAE in GaN HEMT Technology. Ph.D. Research in Mcroelectronics and Electronics (PRIME), 1-4.
[3] Hwang, T., Lin, J., Azadet, K., Wilson, R.S., Kiss, P., Abdelli, S. and Laturell, D. (2013) Class-F Power Amplifier with 80.1% Maximum PAE at 2 GHzJor Cellular Basestation Applications. IEEE 14th Annual on Wireless and Microwave Technology Conference (WAMICON), 1-3.
[4] Thian, M., Barakat, A. and Fusco, V. (2015) High-Efficiency Harmoic-Peaking Class-EF Power Amplifiers with Enhanced Maximum Operating Frequency. IEEE Transactions on Microwave Theory and Techniques, 63, 659-671. http://dx.doi.org/10.1109/TMTT.2014.2386327

Copyright © 2024 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.