Algorithmic Optimization of BDDs and Performance Evaluation for Multi-level Logic Circuits with Area and Power Trade-offs
Saurabh Chaudhury, Anirban Dutta
DOI: 10.4236/cs.2011.23031   PDF    HTML     5,321 Downloads   8,901 Views   Citations


Binary Decision Diagrams (BDDs) can be graphically manipulated to reduce the number of nodes and hence the area. In this context, ordering of BDDs play a major role. Most of the algorithms for input variable ordering of OBDD focus primarily on area minimization. However, suitable input variable ordering helps in minimizing the power consumption also. In this particular work, we have proposed two algorithms namely, a genetic algorithm based technique and a branch and bound algorithm to find an optimal input variable order. Of course, the node reordering is taken care of by the standard BDD package buddy-2.4. Moreover, we have evaluated the performances of the proposed algorithms by running an exhaustive search program. Experi-mental results show a substantial saving in area and power. We have also compared our techniques with other state-of-art techniques of variable ordering for OBDDs and found to give superior results.

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S. Chaudhury and A. Dutta, "Algorithmic Optimization of BDDs and Performance Evaluation for Multi-level Logic Circuits with Area and Power Trade-offs," Circuits and Systems, Vol. 2 No. 3, 2011, pp. 217-224. doi: 10.4236/cs.2011.23031.

Conflicts of Interest

The authors declare no conflicts of interest.


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