Logical Function Decomposition Method for Synthesis of Digital Logical System Implemented with Programmable Logic Devices (PLD)

Mihai Grigore Timis, Alexandru Valachi, Alexandru Barleanu, Andrei Stan

Automatic Control and Computer Engineering Faculty, Technical University Gh.Asachi, Iasi, Romania.

DOI: 10.4236/cs.2013.47062                

Abstract

The paper consists in the use of some logical functions decomposition algorithms with application in the implementation of classical circuits like SSI, MSI and PLD. The decomposition methods use the Boolean matrix calculation. It is calculated the implementation costs emphasizing the most economical solutions. One important aspect of serial decomposition is the task of selecting “best candidate” variables for the G function. Decomposition is essentially a process of substituting two or more input variables with a lesser number of new variables. This substitutes results in the reduction of the number of rows in the truth table. Hence, we look for variables which are most likely to reduce the number of rows in the truth table as a result of decomposition. Let us consider an input variable purposely avoiding all inter-relationships among the input variables. The only available parameter to evaluate its activity is the number of “l”s or “O”s that it has in the truth table. If the variable has only “1” s or “0” s, it is the “best candidate” for decomposition, as it is practically redundant.

Keywords

Combinational Circuits; Static Hazard; Logic Design; Boolean Functions; Logical Decompositions

Conflicts of Interest

The authors declare no conflicts of interest.

References

[1]	[1] M. Denouette, J. P. Perrin and E. Daclin, “Systemès Logiques,” Tome I, Dunod, Paris, 1967, pp. 4-56.
[2]	C. H. Roth, “Fundamentals of Logic Design,” West Publishing Company, Eagan, 1999, pp. 148-172.
[3]	Al. Valachi, Fl. Hoza, V. Onofrei and R. Silion, “Analiza, Sinteza si Testarea Dispozitivelor Numerice,” Nord-Est, 1993, pp. 31-32; 45-53.
[4]	J. A. Brzozowski and T. Luba, “Decomposition of Boolean Functions Specified by Cubes,” Journal of Multiple-Valued Logic and Soft Computing, Vol. 9, 2003.
[5]	M. Rawski, “Decomposition of Boolean Function Sets,” Electronics and Telecommunications Quarterly, Vol. 53, No. 3, 2007, pp. 231-249.
[6]	J. A. Brzozowski and T. Luba, “Logic Decomposition Aimed at Programmable Cell Arrays,” International Conference of Microelectronics: Microelectronics, Vol. 1783, 1992, pp. 77-88. http://dx.doi.org/10.1117/12.130993
[7]	S. J. E. Wilton, “SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays,” FPGA, 1998, pp. 171-178.
[8]	“Logic Synthesis Strategy for FPGAs with Embedded Memory Blocks,” Mariusz Rawski, Grzegorz Borowik, Tadeusz Luba, Pawel Tomaszewicz, Bogdan j. Falkowski. Przeglad Elektrotechnic Znyelectrical Review), R. 86 NR 11a/2010.