Dynamic and Leakage Power Estimation in Register Files Using Neural Networks


Efficient power consumption and energy dissipation in embedded devices and modern processors is becoming increasingly critical due to the limited energy supply available from the current battery technologies. It is vital for chip architects, circuit, and processor designers to evaluate the energy per access, the power consumption and power leakage in register files at an early stage of the design process in order to explore power/performance tradeoffs, and be able to adopt power efficient architectures and layouts. Power models and tools that would allow architects and designers the early prediction of power consumption in register files are vital to the design of energy-efficient systems. This paper presents a Radial Base Function (RBF) Artificial Neural Network (ANN) model for the prediction of energy/access and leakage power in standard cell register files designed using optimized Synopsys Design Ware components and an UMC 130 nm library. The ANN model predictions were compared against experimental results (obtained using detailed simulation) and a nonlinear regression-based model, and it is observed that the ANN model is very accurate and outperformed the nonlinear model in several statistical parameters. Using the trained ANN model, a parametric study was carried out to study the effect of the number of words in the file (D), the number of bit in one word (W) and the total number of Read and Write Ports (P) on the values of energy/access and the leakage power in standard cell register files.

Share and Cite:

A. Sagahyroon and J. Abdalla, "Dynamic and Leakage Power Estimation in Register Files Using Neural Networks," Circuits and Systems, Vol. 3 No. 2, 2012, pp. 119-125. doi: 10.4236/cs.2012.32016.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] N. Sung and T. Mudge, “The Micorarchitecure of a Low Power Register File,” Proceedings of the International Symposium on Low Power Electronics and Design, Seoul, 25-27 August 2003, pp. 384-389.
[2] X. Guan and Y. Fei, “Reducing Power Consumption of Embedded Processors through File Partitioning and Compiler Support,” Proceedings of the Conference on Application-Specific Systems, Architecture and Processors (ASAP), Leuven, 2-4 July 2008, pp. 269-274.
[3] Y. Zhou, H. Guo and J. Gu, “Register File Customization for Low Power Embedded Processors,” IEEE International Conference on Computer Science and Information Technology, Beijing, 8-11 August 2009, pp. 92-96. doi:10.1109/ICCSIT.2009.5234988
[4] M. Kondo and H. Nakamura, “A Small, Fast and LowPower Register File by Bit-Partitioning,” 11th International Symposium on High-Performance Computer Architecture, San Francisco, 12-16 February 2005, pp. 40-49. doi:10.1109/HPCA.2005.3
[5] M. Mueller et al, “Low Power Register File Architecture for Application Specific DSPs,” IEEE International Symposium on Circuits and Systems, 2002, Vol. 4, pp. 89-92.
[6] S. Wang, H. Yang, J. Hu and S. G. Ziavras, “Asymmetrically Banked Value-Aware Register Files for Low-Energy and High-Performance,” Microprocessors and Microsystems, Vol. 32, No. 3, 2008, pp. 171-182. doi:10.1016/j.micpro.2007.10.004
[7] H. Takamura, K. Inoue and V. G. Moshnyaga, “Reducing Access Count to Register Files through Operand Reuse,” Advances in Computer Architecture, Lecture Notes in Computer Science, Vol. 2823, 2003, pp. 112-121. doi:10.1007/978-3-540-39864-6_10
[8] W.-Y. Shieh, H.-D. Chen, “Saving Register-File Static Power by Monitoring Instruction Sequence in ROB,” Journal of Systems Architecture, Vol. 57, No. 4, 2011, pp. 327-339. doi:10.1016/j.sysarc.2011.02.004
[9] J. H. Tseng and K. Asanovic, “Energy-Efficient Register Access,” 13th Symposium on Integrated Circuits and System Design, Manaus, 18 September 2000, pp. 377-382.
[10] P. Raghavan, A. Lambrechts, M. Jayapala, F. Catthoor and D. Verkest, “EMPIRE: Empirical Power/Area/Timing Models for Register Files,” Microprocessors and Microsystems, Vol. 33, No. 4, 2009, pp. 295-300. doi:10.1016/j.micpro.2009.02.009
[11] D. Brooks, V. Tiwari and M. Martonosi, “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations,” Proceedings of the 27th International Symposium on Computer Architecture, Vancouver, 14 June 2000, pp. 83-94.
[12] N. Kahraman and T. Yildirim, “Technology independent circuit sizing for standard cell based design using neural Etworks,” Digital Signal Processing, Vol. 19, No. 4, 2009, pp. 708-714. doi:10.1016/j.dsp.2008.11.009
[13] F. Djeffal, M. Chahdi, A. Benhaya and M. L. Hafiane, “An Approach Based on Neural Computation to Simulate the Nanoscale CMOS Circuits: Application to the Simulation of CMOS Inverter,” Solid-State Electronics, Vol. 51, No. 1, 2007, pp. 48-56. doi:10.1016/j.sse.2006.12.004
[14] P. Kalpana and K. Gunavathi, “Wavelet Based Fault Detection in Analog VLSI Circuits Using Neural Networks,” Applied Soft Computing, Vol. 8, No. 4, 2008, pp. 15921598. doi:10.1016/j.asoc.2007.10.023
[15] A. Suissa, O. Romain, J. Denoulet, K. Hachicha and P. Garda, “Empirical Method Based on Neural Networks for Analog Power Modeling,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 5, 2010, pp. 839-844. doi:10.1109/TCAD.2010.2043759
[16] D. Dhabak and S. Pandit, “An Artificial Neural Network-Based Approach for Performance Modeling of Nano-Scale CMOS Inverter,” Institute of Engineering and Management Conference, January 2011, pp. 165-170.
[17] S. Haykin, “Neural Networks: A Comprehensive Foundation,” 2nd Edition, Prentice-Hall, Upper Saddle River, 1999.
[18] J. A. Abdalla and R. Hawileh, “Modeling and Simulation of Low-Cycle Fatigue Life of Steel Reinforcing Bars Using Artificial Neural Network,” Journal of the Franklin Institute, Vol. 348, No. 7, 2011, pp. 1393-1403. doi:10.1016/j.jfranklin.2010.04.005

Copyright © 2024 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.