A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices
Jin Young Choi
DOI: 10.4236/cn.2010.21002   PDF    HTML     8,417 Downloads   14,356 Views   Citations


For three fundamental input-protection schemes suitable for high-frequency CMOS ICs, which utilize protection devices such as NMOS transistors, thyristors, and diodes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit model of input HBM test environments for CMOS chips equipped with input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the peak voltage developed in the later stage of discharge, which corresponds to the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain strength and weakness of each protection scheme as an input ESD protection circuit for high-frequency ICs, and suggest valuable guidelines relating design of the protection devices and circuits.

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J. Choi, "A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices," Communications and Network, Vol. 2 No. 1, 2010, pp. 11-25. doi: 10.4236/cn.2010.21002.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] P. Leroux and M. Steyaert, “High-performance 5.2GHz LNA with on-chip inductor to provide ESD protection,” Electronics Letters, Vol. 37, pp. 467–469, March 2001.
[2] B. Kleveland, T. J. Maloney, I. Morgan, L. Madden, T. H. Lee, and S. S. Wong, “Distributed ESD protection for high-speed integrated circuits,” IEEE Transactions on Electron Devices, Vol. 21, pp. 390–392, August 2000.
[3] S. Hyvonen, S. Joshi, and E. Rosenbaum, “Cancellation technique to provide ESD protection for multi-GHz RF inputs,” Electronic Letters, Vol. 39, No. 3, pp. 284–286, February 2003.
[4] A. Chatterjee and T. Polgreen, “A low-voltage triggering SCR for on-chip ESD protection at output and input pads,” IEEE Electron Device Letters, Vol. 12, pp. 21–22, August 1991.
[5] E. R. Worley, R. Gupta, B. Jones, R. Kjar, C. Nguyen, and M. Tennyson, “Sub-micron chip ESD protection schemes which avoid avalanching junctions,” in Processing, EOS/ ESD Symposium, pp. 13–20, 1995.
[6] H. Feng, G. Chen, R. Zhan, Q. Wu, X. Guan, H. Xie, and A. Z. H. Wang, “A mixed-mode ESD protection circuit simulation-design methodology,” IEEE Journal Soilid- State Circuits, Vol. 38, pp. 995–1006, June 2003.
[7] B. Fankhauser and B. Deutschmann, “Using device simulations to optimize ESD protection circuits”, in Processing, IEEE EMC Symposium, pp. 963–968, 2004.
[8] ATLAS II Framework, Version 5.10.2.R, Silvaco International, 2005.
[9] A. Amerasekera, L. van Roozendaal, J. Bruines, and F. Kuper, “Characterization and modeling of second breakdown in nMOST’s for extraction and ESD-related process and design parameters,” IEEE Transactions on Electron Devices, Vol. 38, pp. 2161–2168, September 1991.
[10] C. H. Diaz, S. M. Kang, and C. Duvvury, “Modeling of electrical overstress in integrated circuit,” Kluwer Academic Publishers, 1995.
[11] Z. H. Liu, E. Rosenbaum, P. K. Ko, C. Hu, Y. C. Cheng, C. G. Sodini, B. J. Gross, and T. P. Ma, “A comparative study of the effect of dynamic stressing on high-field endurance and stability of reoxidized-nitrided, fluorinated and conventional oxides,” in IEDM Technology Digest, pp. 723–726, 1991.
[12] G. Chen, H. Fang, and A. Wang, “A systematic study of ESD protection structures for RF ICs,” in Processing, IEEE Radio Frequency Integrated Circuit Symposium, Vol. 46, pp. 347–350, 2003.
[13] J. Y. Choi, “AC modeling of the ggNMOS ESD protection device,” ETRI Journal, Vol. 27, No. 5, pp. 628–634, October 2005.

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