1. Introduction
This paper represents combination of two main units:
• Memory wrapper for increasing flexibility of designing memory-integrated designs.
• Top level BIST method which can reduce testing time of the whole system in one wrapper.
The memory wrapping method commonly used in the VLSI [1] [2] [3] : the main disadvantage of existing methods [1] [4] is that the memory wrapper concatenates only memories with the same bit sizes. In other words, the old memory wrappers extend the memory size (capacitance) but not bit size [5] . The standard memory wrapper structures combine concatenation of memory address and simple memory selecting method and the same selecting method is used for memory input and output data pins (Figure 1).
Basic memory wrapper consists of few elements:
• U1 unit is combined memories provided from foundry,
• U2 and U3 are the address decoder and memory select decoder,
• U4 is the logical unit which controls data input distribution between memories,
• U5 is the logical unit which controls data output distribution between memories.
The schematic model of U2 and U3 is address decoder, U4 and U5 functionality is the same, both modules selecting connection between wrapper input/output and memory which have been selected based on U3.
The input of U2 and U3 can be combined as address select. With correct concatenation and distribution of the memory pins (clock, write enable, read enable, etc.), the wrapper can be fully functional unit. After above mentioned transformation, the memory wrapper can be used as single memory in the different designs.
Basic BIST for memories has been created for finding broken cells in the memory by writing and reading data bits into/from memory cells [5] . Moreover, mapping of the broken cell address into the reserved memory block addresses is the biggest advantage of the BIST. In other words, the memory BIST directly increases yield of the memory module by additional memory cell mapping. The main disadvantage of the BIST is the power consumption while testing memory cells [6] . BIST core is combination of testing engine and reserved memory (Figure 2).
Following is the unit (marked as U) and pin (marked as P) description for Figure 2.
1) MUT―The memory which is under test.
2) BIST consists of few units:
a) Address generator―Unit for address list generation, which will be given to memory under test (MUT);
b) Data generator―Unit for generating test data to be given to MUT as input;
c) Comparator―Unit to compare generated data with MUT outputted data from under test address;
d) Memory array―Unit for storing data lines which were supposed to be written in broken addresses of MUT;
e) BIST core―Unit for controlling all above mentioned 4 units’ works and mapping broken data line addressed of MUT to memory array addresses.
This module has 2 main working modes:
1) BIST mode―to test MUT and remap broken addresses. This mode is self-working mode and does not have connection with external pins.
2) Use mode―to unable the BIST test/repair functionality and leave mapping functionality only. In this mode external pins are being used as Address input and Data input/output.
Modes can be switched with BIST Enable (BE) input signal.
The main aim of having BIST is having ability to check memory cells by writing and reading in/from each cell. For this matter, BIST is writing and reading different values (either logic 0 or logic 1) to be able to cover cases of stacked 0 and stacked 1 in cell. If broken cell is found and there is empty (not linked) cell address in BIST’s memory array, BIST core will link broken address of proposed memory cell to BIST memory array address.
Based on memory size, upper mentioned BIST run process can take long initialization time. In memory dominant designs, parallel BIST process can lead to die overheating, which can cause to broken chip.
To overcome overheating and long runtime issues under BIST mode, quasi-parallel BIST implementation can be used. Technic is called quasi-parallel as at each period of BIST, some counts of memories are in test mode, while others are in waiting mode. Main constraint of quasi-parallel BIST is to ensure that on each period of BIST, under-test memories are enough far from each other, in point of physical placement, to prevent chip from local overheating.
2. BIST Control-Based Wrapper
Above mentioned issue can be solved using BIST control logic with multiple memories, which are already integrated with BIST. BIST control logic will enable BIST mode on some amount of memories base on wrapper compile process selected option (Figure 3).
Wrapper contains 3 main units:
• BIST control―Unit to control BIST mode selection process and concatenate memories and addresses, data input/output (makes system as one memory);
• Standard stand-alone BIST―Upper mentioned standard memory BIST;
• Memory under test―Foundry provided memories.
The option which is selected in compilation time (the amount of parallel-checked memories) will bring to internal grouping of memories, which must be under parallel BIST run. Memories from one internal group must be placed with bigger distance while physical placement process and this will prevent local overheating.
3. Top Level BIST Algorithm
Top level BIST algorithm has two main components (Figure 4):
1) Commonly used BIST methodology for one memory that is integrated with already wrapped memories. This method is the same as memory BIST but addresses and data sizes are extended (wrapped memories). Difference with common BIST is that in top level BIST algorithm BIST is divided into two separate process: checking and repairing.
a) Checking―Checking if the memory cell is working.
b) Repairing―Mapping memory address to BIST backup array.
2) Internal memory BIST enablement core―After checking process this algorithm gets memories with non-working cells as input and enables internal BIST
for them. Once internal BIST is done the TOP level BIST is running again, but this time combined with repairing process.
In Figure 4 can be possible two scenarios:
1) After Top level BIST check all memories are working correctly. In this case no need more action, this scenario is the best in terms of testing time;
2) After Top level BIST check there are memories which need cell address mapping. This scenario will pass through all units mentioned in Figure 4 starting from memory BIST check until memory BIST repair (memory BIST check ?> internal memory BIST enablement core ?> memory BIST check ?> memory BIST rapier).
4. Memory Grouping Wrapper with Top Level BITS Algorithm
Memory grouping wrapper with top level BIST algorithm is the integration of top level BIST algorithm and BIST control-based wrapper. Main difference of this method compared with one memory BIST method is that BIST core logic combines wrapper grouping methodology and internal memory BIST enablement core (Figure 5).
On the other hand, top level BIST can be interpreted as single memory BIST, if memories address and data are combined. Only need to be under consideration BE enablement signal of memories on top level BIST.
Memory grouping wrapper with TOP level BIST contains:
1) Memories under test,
2) Single memory BIST units,
3) TOP BIST unit with BIST core.
5. Testing Results
For testing BIST, selected MARCH C algorithm as a reference and implemented MARCH C for memory and top-level BIST. Implementation has been tested in
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Figure 5. Memory grouping wrapper with top level BIST block diagram.
the Xilinx Inc spartan 6 FPGA with constricted same 64x8 memory cell. Results are shown in Table 1.
New architecture has approximately 13% more STD cells and memory testing time increases by 22% and added approximately 3% more redundancy addresses. The redundancy addresses bring additional reliability in the memory System.
6. Conclusion
This technique brings additional relatability in the memory system. According to the test results using this method memory testing time will be increased, but the memory system will get additional top-level memory BIST. Based on test results top-level BIST brings 3% more redundancy addresses. Results are expected as we are adding more redundancy addresses.