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Comparison and Design of Decoder in B3G Mobile Communication System

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DOI: 10.4236/cn.2009.11003    4,694 Downloads   8,480 Views   Citations


Turbo code has been shown to have ability to achieve performance that is close to Shannon limit. It has been adopted by various commercial communication systems. Both universal mobile telecommunications system (UMTS) TDD and FDD have also employed turbo code as the error correction coding scheme. It outperforms convolutional code in large block size, but because of its time delay, it is often only used in the non-real-time service. In this paper, we discuss the encoder and decoder structure of turbo code in B3G mobile communication System. In addition, various decoding techniques, such as the Log-MAP, Max-log-MAP and SOVA algorithm for non-real-time service are deduced and compared. The performance results of decoder and algorithms in different configurations are also shown.

Conflicts of Interest

The authors declare no conflicts of interest.

Cite this paper

M. GUAN and M. YANG, "Comparison and Design of Decoder in B3G Mobile Communication System," Communications and Network, Vol. 1 No. 1, 2009, pp. 20-24. doi: 10.4236/cn.2009.11003.


[1] PIETROBON S S. Implementation and performance of a turbo/ MAP decoder. Int. J. Satellite Communication, 1998, 16: 23-46.
[2] KAZA J, CHAKRABARTI C. Design and implementation of low-energy turbo decoders. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004, 12(9): 968-977.
[3] HAGH M, SALEHI M, ET AL. Implementation issues in turbo decoding for 3GPP FDD receiver. Wireless Personal Communi- cations, 2006, 39(2): 165-182.
[4] LEE D-S, PARK I.-C. Low-power log-MAP decoding based on reduced metric memory access. IEEE Transactions on Circuits and Systems, 2006, 53(6): 1244-1253.
[5] BOUTILLON E, GROSS W J, GULAK P G. VLSI architectures for the MAP algorithm. IEEE Transactions on Communications, 2003, 51(2): 175-185.
[6] ANANTHARAM V E Y. Iterative decoder architectures. IEEE Communications Magazine, 2003, 41(8): 132-140.
[7] KWON T-W, CHOI J-R. Implementation of a two-step SOVA decoder with a fixed scaling factor. IEICE Transactions on Communications, E86-B(6): Jun. 2003, 1893-1900.
[8] CHEN Y, PARHI K K. On the performance and imple- mentation issues of interleaved single parity check turbo product codes. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 2005, 39(1): 35-47.

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