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Ultra-Low Power Designing for CMOS Sequential Circuits

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DOI: 10.4236/ijcns.2015.85016    3,367 Downloads   3,927 Views   Citations

ABSTRACT

Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Many power reduction techniques have also been proposed from the system level down to the circuit level. High-speed computation has thus become the expected norm from the average user, instead of being the province of the few with access to a powerful mainframe. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Techniques for low-power operation are shown in this paper, which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. The threshold vol-tages of the MTCMOS devices for both low and high Vth are constructed as the low threshold Vth is approximately 150 - 200 mv whereas the high threshold Vth is managed by varying the thickness of the oxide Tox. Hence we are using different threshold voltages with minimum voltages and hence considered this project as ultra-low power designing.

Conflicts of Interest

The authors declare no conflicts of interest.

Cite this paper

Sreenivasulu, P. , Rao, S. and Babu, V. (2015) Ultra-Low Power Designing for CMOS Sequential Circuits. International Journal of Communications, Network and System Sciences, 8, 146-153. doi: 10.4236/ijcns.2015.85016.

References

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http://dx.doi.org/10.1109/4.400426
[2] Shigematsu, S., et al. (1995) A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Applications. Symposium on VLSI Circuits, Kyoto, 8-10 June 1995, 125-126.
[3] Kuroda, T., et al. (1996) A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme. IEEE International Solid-State Circuits Conference, New York, February 1996, 166-167.
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[6] Makino, H., Tsujihashi, Y., Nii, K., Morishima, C., Hayakawa, Y., Shimizu, T. and Arakwa, A. (1998) An Auto-Backgate-Controlled MT-CMOS Circuit. Symposium on VLSI Circuits, Honolulu, 11-13 June 1998, 42-43.
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http://dx.doi.org/10.1109/4.126534
[9] Horiguchi, M., Sakata, T. and Itoh, K. (1993) Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-Scale LSI’s. IEEE Journal of Solid-State Circuits, 28, 1131-1135.
http://dx.doi.org/10.1109/4.245593
[10] Kawahara, T., Horiguchi, M., Kawajiri, Y., Kitsukawa, G., Kure, T. and Aoki, M. (1993) Subthreshold Current Reduction for Decoded-Driver by Self-Reverse Biasing. IEEE Journal of Solid-State Circuits, 28, 1136-1144.
http://dx.doi.org/10.1109/4.245594
[11] Mutoh, S., Douseki, T., Matsuya, Y., Aoki, T. and Yamada, L. (1993) 1V High-Speed Digital Circuit Technology with 0.5-μm Multi Threshold CMOS. Proceedings of 6th Annual IEEE International ASIC Conference and Exhibit, Rochester, 27 September-1 October 1993, 186-189.
[12] Sreenivasulu, P., Srinivasa Rao, K. and Vinayababu, A. (2011) Power Optimization in Digital Circuits through Leakage Current Reduction by Using Multi Threshold CMOS. International Journal of VLSI Signal Processing Applications, 1, No. 5.
[13] Kao, J.T. and Chandrakasan, A.P. (2000) Dual-Threshold Voltage Techniques for Low-Power Digital Circuits. IEEE Journal of Solid-State Circuits, 35, 1009-1018.
[14] Shigematsu, S., et al. (1997) A 1-V High Speed MTCMOS Circuit Scheme for Power-DOWN Application Circuits. IEEE Journal of Solid-State Circuits, 32, 861-869.
[15] Mutoh, S., et al. (1995) 1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS. IEEE Journal of Solid-State Circuits, 30, 847-854.
http://dx.doi.org/10.1109/4.400426
[16] Shigematsu, S., et al. (1995) A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Applications. Symposium on VLSI Circuits, Kyoto, 8-10 June 1995, 125-126.
[17] Kuroda, T., et al. (1996) A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme. IEEE International Solid-State Circuits Conference, New York, February 1996, 166-167.
[18] Shimizu, T., et al. (1996) A Multimedia 32b RISC Microprocessor with 16Mb DRAM. 1996 IEEE International Solid-State Circuits Conference, San Jose, February 1996, 216-217.
[19] Kumagai, K., Iwaki, H., Yoshida, H., Suzuki, H., Yamada, T. and Kurosawa, S. (1998) A Novel Powering-Down Scheme for Low Vt CMOS Circuits. Symposium on VLSI Circuits, Honolulu, 11-13 June 1998, 44-45.
[20] Makino, H., Tsujihashi, Y., Nii, K., Morishima, C., Hayakawa, Y., Shimizu, T. and Arakwa, A. (1998) An Auto-Backgate-Controlled MT-CMOS Circuit. Symposium on VLSI Circuits, Honolulu, 11-13 June 1998, 42-43.
[21] Brodersen, R.W., Chandrakasan, A. and Sheng, S. (1993) Design Techniques for Portable Systems. IEEE International Solid-State Circuits Conference, San Jose, February 1993, 168-169.
[22] Chandrakasan, A.P., Sheng, S. and Brodersen, R.W. (1992) Low-Power CMOS Digital Design. IEEE Journal of Solid-State Circuits, 27, 473-484.
http://dx.doi.org/10.1109/4.126534
[23] Horiguchi, M., Sakata, T. and Itoh, K. (1993) Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-Scale LSI’s. IEEE Journal of Solid-State Circuits, 28, 1131-1135.
http://dx.doi.org/10.1109/4.245593
[24] Kawahara, T., Horiguchi, M., Kawajiri, Y., Kitsukawa, G., Kure, T. and Aoki, M. (1993) Subthreshold Current Reduction for Decoded-Driver by Self-Reverse Biasing. IEEE Journal of Solid-State Circuits, 28, 1136-1144.
http://dx.doi.org/10.1109/4.245594
[25] Mutoh, S., Douseki, T., Matsuya, Y., Aoki, T. and Yamada, L. (1993) 1V High-Speed Digital Circuit Technology with 0.5-μm Multi Threshold CMOS. Proceedings of 6th Annual IEEE International ASIC Conference and Exhibit, Rochester, 27 September-1 October 1993, 186-189.
[26] Sreenivasulu, P., Srinivasa Rao, K. and Vinayababu, A. (2011) Power Optimization in Digital Circuits through Leakage Current Reduction by Using Multi Threshold CMOS. International Journal of VLSI Signal Processing Applications, 1, No. 5.
[27] Kao, J.T. and Chandrakasan, A.P. (2000) Dual-Threshold Voltage Techniques for Low-Power Digital Circuits. IEEE Journal of Solid-State Circuits, 35, 1009-1018.
[28] Shigematsu, S., et al. (1997) A 1-V High Speed MTCMOS Circuit Scheme for Power-DOWN Application Circuits. IEEE Journal of Solid-State Circuits, 32, 861-869.

  
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