An IEEE 1149.x Embedded Test Coprocessor


This paper describes a microprogrammed architecture for an embedded coprocessor that is able to control IEEE 1149.1 to IEEE 1149.7 test infrastructures, and explains how to expand the supported test command set. The coprocessor uses a fast simplex link (FSL) channel to interface a 32-bit MicroBlaze CPU, but it can work with any microprocessor core that accepts this simple FIFO-based interface method. The implementation cost (logic resource usage for a Xilinx Spartan-6 FPGA) and the performance data (operating frequency) are presented for a test command set comprising two parts: 1) the full IEEE 1149.1 structural test operations; 2) a subset of IEEE 1149.7 operations selected to illustrate the implementation of advanced scan formats.

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Gebremeskel, U. and Ferreira, J. (2014) An IEEE 1149.x Embedded Test Coprocessor. Circuits and Systems, 5, 170-180. doi: 10.4236/cs.2014.57019.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] (2001) IEEE Standard Test Access Port and Boundary Scan Architecture. IEEE Std 1149.1-2001, 212 p.
[2] (2009) IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture. IEEE Std 1149.7-2009, 985.
[3] Ley, A.W. (2009) Doing More with Less—An IEEE 1149.7 Embedded Tutorial: Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture. International Test Conference, Austin, 1-6 November 2009, 1-10.
[4] Williams, M. (2009) Low Pin-Count Debug Interfaces for Multi-Device Systems. ARM White Paper.
[5] Fernandes, F.R., Machado, R.J.S., Ferreira, J.M.M. and Gericota, M.G.O. (2012) IEEE Std 1149.7: What, Why, Where? Proceedings of the 27th Conference on Design of Circuits and Integrated Systems, Avignon, 28-30 November 2012, 118-123.
[6] Ungar, L.Y., Bleeker, H., McDermid, J.E. and Hulvershorn, H. (2001) IEEE-1149.x Standards: Achievements vs. Expectations. IEEE Systems Readiness Technology Conference, Valley Forge, 20-23 August 2001, 188-205.
[7] IEEE Standard for Module Test and Maintenance Bus (MTM-Bus) Protocol (1996) IEEE Std 1149.5-1995.
[8] IEEE Standard for a Mixed-Signal Test Bus (1999) IEEE Std 1149.4-2010 (Revision of IEEE Std 1149.4-1999).
[9] IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks (2003) IEEE Std 1149.6-2003.
[10] Serial Vector Format Specification (1994) Revision E.
[11] Lynch, M.A. (1993) Microprogrammed State Machine Design. CRC Press, Boca Raton.
[12] Yau, C.W. and Jarwala, N. (1990) The Boundary-Scan Master: Target Applications and Functional Requirements. Proceedings of the IEEE International Test Conference, Washington DC, 10-14 September 1990, 311-315.
[13] Ferreira, J.M., Matos, J.S. and Pinto, F.S. (1992) Automatic Generation of a Single-Chip Solution for Board-Level BIST of Boundary Scan Boards. Proceedings of the European Design Automation Conference, Brussels, 16-19 March 1992, 154-158.
[14] SN54ACT8990, SN74ACT8990, IEEE STD 1149.1 (JTAG) TAP Masters with 16-Bit Generic Host Interfaces (1997) Texas Instruments Datasheet.
[15] Chen, S.J., Zhou, Y., Zhu, D.X. and Guo, S.L. (2011) Design of High-Speed Boundary-Scan Master Controller Base on SOPC. Proceedings of the 2nd International Conference on Mechanic Automation and Control Engineering, Hohhot, 15-17 July 2011, 1195-1198.
[16] Kaur, M. and Singh, B. (2012) VHDL Implementation of Test Access Port Controller. International Journal of Engineering Science and Technology (IJEST), 4.
[17] Cabral, C.J. (2012) Design and Implementation of an IEEE 1149.7-Compliant cJTAG Controller for Debug and Trace Probe. Master of Science in Engineering Report, University of Texas at Austin, Austin, 55 p.

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