High-Throughput and Area-Efficient FPGA Implementations of Data Encryption Standard (DES)


One of the most popular standards for protecting confidential information is the Data Encryption Standard (DES). Although it has been replaced by the Advanced Encryption Standard (AES), it is still widely used in Automatic Teller Machines (ATM’s), smartcards, and mobile phone SIM cards. In this paper, we present area-efficient and high-throughput FPGA implementations of the DES which are developed using the Xilinx FPGA ISE design suite. In fact, we propose modifications on the fastest DES design reported in the literature and achieve 1.1 times higher speed. Also, we introduce an 8-stage pipelined design that needs only 0.75 times the registers and consumes 0.65 times the power of a similar 16-stages pipelined design. High-speed design and synthesis optimization techniques including pipelining, register retiming, and logic replication are used. Post- layout synthesis results show that the proposed implementations achieve high throughput-to-area ratio. To make a fair comparison, the proposed designs were synthesized using matching FPGA devices as being used by other implementations reported in the literature.

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Bani-Hani, R. , Harb, S. , Mhaidat, K. and Taqieddin, E. (2014) High-Throughput and Area-Efficient FPGA Implementations of Data Encryption Standard (DES). Circuits and Systems, 5, 45-56. doi: 10.4236/cs.2014.53007.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] Saqib, N.A., Rodriguez-Henriquez, F. and Diaz-Pierez, A. (2004) A compact and efficient FPGA implementation of the DES algorithm. International Conference on Reconfigurable Computing and FPGAs, Colima, 20-21 September 2004, 12-18.
[2] FIPS PUBS 46-3, Federal Information Processing Standards Publication, U.S. Department Of Commerce/National Institute of Standards and Technology, 1999.
[3] American Bankers Association (1986) (Revised): A.X. National Standards for Financial Institution Key Management (Wholesale).
[4] X9.62, A Federal Information Processing Standard (FIPS) 46, National Bureau Standards, 1977.
[5] Chueng, T.P., Yusoff, Z.M. and Shaameri, A.Z. (2000) Implementation of Pipelined Data Encryption Standard (DES) Using Altera CPLD. Proceedings of TENCON 2000, 24-37 September 2000, Kuala Lumpur, 17-21.
[6] NIST: Announcing the Advanced Encryption Standard (AES), Federal Information Standards Publication, 2001.
[7] Taherkhani S., Ever, E. and Gemikonakli, O. (2010) Implementation of Non-Pipelined and Pipelined Data Encryption Standard (DES) Using Xilinx Virtex-6 FPGA Technology. 2010 IEEE 10th International Conference on Computer and Information Technology (CIT), 29 June 2010-1 July 2010, Bradford, 1257-1256.
[8] S. Kelly (2006) Security Implications of Using the Data Encryption Standard (DES), RFC 4772.
[9] Phan, R.C.W. (2007) Reducing the Exhaustive Key Search of the Data Encryption Standard (DES). Computer Standards & Interfaces, 29, 528-530. http://dx.doi.org/10.1016/j.csi.2006.11.010
[10] Nohl, K. (2013) Rooting SIM Cards.
[11] Guilleya, S., Hoogvorsta, P. and Pacaleta, R. (2007) A Fast Pipelined Multi-Mode DES Architecture Operating in IP Representation. Integration, the VLSI Journal, 40, 479-489.
[12] Graf, R.F. and Sheets, W. (1998) Video Scrambling and Descrambling: for Satellite and Cable TV. 3rd Edition, Newnes, Burlington.
[13] Kaps, J.-P. and Paar, C. (1998) Fast DES Implementations for FPGAs and Its Application to a Universal Key-Search Machine. Selected Areas in Cryptography, Lecture Notes in Computer Science, 1556, 234-247
[14] Kilts, S. (2007) Advanced FPGA Design: Architecture, Implementation, and Optimization, 1st Edition, Wiley-IEEE Press, New York. http://dx.doi.org/10.1002/9780470127896
[15] Trimberger, S., Pang, R. and Singh, A. (2000) A 12 Gbps DES Encryptor/Decryptor Core in an FPGA. Proceedings of the 2nd International Workshop on Cryptographic Hardware and Embedded Systems, Worcester, 17-18 August 2000, 156-163.
[16] Spartan®-6 FPGA from Xilinx. http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/
[17] Forouzan, B.A. (2008) Introduction to Cryptography and Network Security. McGraw-Hill, New York.
[18] Stallings, W. (2010) Network Security Essentials: Applications and Standards. 4th Edition, Prentice Hall, Englewood Cliff.
[19] Wong, K., Wark, M. and Dawson, E. (1998) A Single-Chip FPGA Implementation of the Data Encryption Standard (DES) Algorithm. IEEE Global Telecommunications Conference on the Bridge to Global Integration, 8-12 November 1998, Sydney, 827-832.
[20] Patterson, C. (2000) High Performance DES Encryption in Virtex FPGAs using JBits. Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, 17-19 April 2000, 113-121.
[21] Broscius, A.G. and Smith, J.M. (1992) Exploiting Parallelism in Hardware Implementations of the DES. Proceedings of the 11th Annual International Cryptology Conference on Advances in Cryptology, 576, 367-376.
[22] McLoone, M. and McCanny, J.V. (2000) High-performance FPGA Implementation of DES. IEEE Workshop on Signal Processing Systems, Lafayette, 11-13 October 2000, 374-383.
[23] Rouvroy, G., Standaert, F.-X., Quisquater, J.-J. and Legat, J. (2003) Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Cryptanalysis. IEEE Transactions on Computers, 52, 473-482.
[24] Services, A.E. (2008) DES and DES3 Encryption Engine.
[25] Standaert, F.-X., Rouvroy, G. and Quisquater, J.-J. (2006) FPGA Implementations of the DES And Triple-Des Masked against Power Analysis Attacks. International Conference on Field Programmable Logic and Applications, 28-30 August 2006, Madrid, 1-4.

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