On the Operation of CMOS Active-Cascode Gain Stage

Yun Chiu

Analog and Mixed-Signal Lab, Texas Analog Center of Excellence, University of Texas at Dallas, Richardson, Texas, USA.

DOI: 10.4236/jcc.2013.16004                

Abstract

An s-domain analysis of the full dynamics of the pole-zero pair (frequency doublet) associated with the broadly used CMOS active-cascode gain-enhancement technique is presented. Quantitative results show that three scenarios can arise for the settling behavior of a closed-loop active-cascode operational amplifier depending on the relative locations of the unity-gain frequencies of the auxiliary and the main amplifiers. The analysis also reveals that, although theoretically possible, it is practically difficult to achieve an exact pole-zero cancellation. The analytical results presented here provide theoretical guidelines to the design of CMOS operational amplifiers using this technique.

Keywords

CMOS Operational Amplifier; Gain Enhancement; Active Cascode; Regulated Cascode; Gain Boosting; Pole- Zero Pair; Doublet; Slow Settling

Conflicts of Interest

The authors declare no conflicts of interest.

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