Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study

Mona M. Fouad, Hassanein H. Amer, Ahmed H. Madian, Mohamed B. Abdelhalim

College of Computing and Information Technology, AASTMT, Cairo, Egypt.
Electronics Engineering Department, American University in Cairo, Cairo, Egypt.
Faculty of Engineering, Cairo University, Cairo, Egypt.
Radiation Engineering Department, NCRRT, Cairo, Egypt.

DOI: 10.4236/cs.2013.44049                

Abstract

This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set; this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.

Keywords

Current Mode Logic (CML); CMOS; Testing; Stuck-At Faults

Conflicts of Interest

The authors declare no conflicts of interest.

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