An Explicit Surface-Potential Based Biaxial Strained-Si n-MOSFET Model for Circuit Simulation

Tapas K. Maiti, Animesh Banerjee, Chinmay K. Maiti

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DOI: 10.4236/eng.2010.211111                

Abstract

In this paper, a charge sheet surface potential based model for strained-Si nMOSFETs is presented and validated with numerical simulation. The model considers sub band splitting in the 2-DEG at the top heterointerface in SiGe layer and also the dependence of electron concentration at heterointerface with the gate oxide. The model is scalable with strained-Si material parameters with physically derived flat-band voltages. An explicit relation for surface potential as a function of terminal voltages is developed. The model is derived from regional charge-based approach, where regional solutions are physically derived. The model gives an accurate description of drain current both in the weak and strong inversion regions of operation. The results obtained from the model developed are benchmarked with commercial numerical device simulator and is found to be in excellent agreement.

Keywords

Strained-Si, Heterostructure, 2-DEG, Surface Potential, Regional Approach

Conflicts of Interest

The authors declare no conflicts of interest.

References

[1]	Semiconductor Industry Association, “International Tech- nol-ogy Roadmap for Semiconductors,” SIA, San Jose, 2005.
[2]	C. K. Maiti, S. Chattopadhyay and L. K. Bea, “Strained-Si Heterostructure Field Effect Device,” Taylor & Francis Group LLC, Boca Raton, 2007.
[3]	C. K. Maiti and G. A. Armstrong, “Applications of Silicon-Germanium Hetero-structure Devices,” Institute of Physics Publisher, Bristol, 2001.
[4]	J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald and D. A. Antoniadis, “Strained Silicon MOSFET Technology,” IEEE International Electron Devices Meeting Technical Digest, San Francisco, 8-11 De-cember 2002, pp. 23-26.
[5]	R. W. Keyes, “Explaining Strain in Silicon,” IEEE Circuits & Devices Magazine, Vol. 35, 2002, pp. 36-39.
[6]	J. Welser, J. L. Hoyt, S. Takagi and J. F. Gibbons, “Strain Dependence of the Performance Enhancement in Strained-Si n-MOSFETs,” IEEE International Electron Devices Meeting Technical Digest, San Francisco, 11-14 December 1994, pp. 373-376.
[7]	C. K. Maiti, “Editorial, Special Issue on Strained-Si Heterostructures and Devices,” Solid-State Electronics, Vol. 48, 2004, p. 1255.
[8]	C. K. Maiti, L. K. Bera and S. Chattopadhyay, “Strained-Si Heterostructure Field Effect Transistors,” Semiconductor Science and Technology, Vol. 13, No. 11, 1998, pp. 1225- 1246.
[9]	S.-I. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, S. Nakaharai, T. Numata, J. Koga and K. Uchida, “Sub- Band Structure Engineering for Advanced CMOS Channels,” Solid-State Electronics, Vol. 49, No. 5, 2005, pp. 684-694.
[10]	F. Schaffler, “High-Mobility Si and Ge Structures,” Semi- conductor Science and Technology, Vol. 12, No. 12, 1997, pp. 1515-1549.
[11]	J. Welser, J. L. Hoyt and J. F. Gibbons, “Electron Mobility Enhancement in Strained-Si N-Type Metal-Oxide- Semiconductor Field-Effect Transistors,” IEEE Electron Device Letters, Vol. 15, No. 3, 1994, pp. 100-102.
[12]	D. K. Nayak, J. C. S. Woo, J. S. Park, K. L. Wang and K. P. Macwilliams, “High-Mobility p-Channel Metal-Oxide- Semiconductor Field-Effect Transistor on Strained Si,” Applied Physics Letters, Vol. 62, No. 22, 1993, pp. 2853- 2855.
[13]	M. V. Fischetti and S. E. Laux, “Band Structure, Deformation Potentials, and Carrier Mobility in Strained Si, Ge, and SiGe Alloys,” Journal of Applied Physics, Vol. 88, No. 4, 1996, pp. 2234-2252.
[14]	R. Oberhuber, G. Zandler and P. Vogl, “Subband Structure and Mobility of Two-Dimensional Holes in Strained Si/SiGe MOSFETs,” Physical Review B, Vol. 58, No. 15, 1998, pp. 9941-9948.
[15]	C. K. Maiti, S. K. Samanta, S. Chatterjee, G. K. Dalapati and L. K. Bera, “Gate Dielectrics on Strained-Si/SiGe Heterolayers,” Solid-State Electronics, Vol. 48, No. 8, 2004, pp. 1369-1389.
[16]	K. Joardar, K. K. Gullapalli, C. McAndrew, M. E. Burnham and A. Wild, “An Improved MOSFET Model for Circuit Simulation,” IEEE Transactions on Electron Devices, Vol. 45, No. 1, January 1998, pp. 134-148.
[17]	P. Bendix, P. Rakers, P. Wagh, L. Lemaitre, W. Grabinski, C. C. McAndrew, X. Gu and G. Gildenblat, “RF Distortion Analysis with Compact MOSFET Models,” Proceedings of IEEE Custom Integrated Circuits Conference, Orlando, 3-6 October 2004, pp. 9-12.
[18]	“BSIM3 and BSIM4 Compact MOSFET Model Summary.” http://www-device.eecs.berkeley.edu/~3/get.html
[19]	C. C. Enz, F. Krummenacher and E. A. Vittoz, “An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedi-cated to Low-Voltage and Low-Current Applications,” Analog Integrated Circuits and Signal Processing, Vol. 8, No. 1, July 1995, pp. 83-114.
[20]	G. Gildenblat, X. Li, W. Wu, H. Wang, A. Jha, R. Van Langevelde, G. Smit, A. Scholten and D. Klas-sen, “PSP: An Advanced Surface Potential Based MOSFET Model for Circuit Simulation,” IEEE Transactions on Electron Devices, Vol. 53, No. 9, September 2006, pp. 399-402.
[21]	T.-L. Chen and G. Gildenblat, “Symmetric Bulk Charge Linearization of Charge Sheet MOSFET Model,” Electronics Letters, Vol. 37, No. 12, June 2001, pp. 791-793.
[22]	T.-L. Chen and G. Gildenblat, “Analytical Ap-proximation for the MOSFET Surface Potential,” Solid-State Electronics, Vol. 45, No. 2, February 2001, pp. 335-339.
[23]	M. M. Mattausch, U. Feldmann, A. Rahm, M. Bollu and D. Savignac, “Unified Complete MOSFET Model for Circuit for Analysis of Digital and Analog Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 1, January 1996, pp. 1-7.
[24]	W. Zhang and J. G. Fossum, “On the Threshold Voltage of Strained-Si–Si1 – xGex MOSFETs,” IEEE Transactions on Electron Devices, Vol. 52, No. 2, February 2005, pp. 263-268.
[25]	K. Chandrasekaran, X. Zhou, S. B. Chiah, W. Shangguan and G. H. See, “Physics-Based Single-Piece Charge Model for Strained-Si MOSFETs,” IEEE Transactions on Electron Devices, Vol. 52, No. 7, July 2005, pp. 1555-1562.
[26]	B. Bindu, N. DasGupta and A. DasGupta, “Analytical Model of Drain Current of Si/SiGe Heterostructure p-Channel MOSFETs for Circuit Simulation,” IEEE Transac-tions on Electron Devices, Vol. 53, No. 6, June 2006, pp. 1411-1419.
[27]	Y. L. Tsang, S. Chattopadhyay, S. Uppal, E. Escobedo-Cousin, H. Ramakrishnan, S. H. Olsen and A. G. O’Neill, “Modeling of the Threshold Voltage in Strained Si/Si1 ? xGex/Si1 ? yGey(x ≥ y) CMOS Architectures,” IEEE Transac-tions on Electron Devices, Vol. 54, No. 11, November 2007, pp. 3040-3048.
[28]	E. Kasper and D. J. Paul, “Silicon Quantum Integrated Circuits,” Springer-Verlag, Berlin, 2005.
[29]	M. M. Rieger and P. Vogl, “Electronic-Band Parameters in Strained Si1 – xGex Alloys on Si1 – yGey Substrate,” Physical Review B, Vol. 48, No. 19, 1993, pp. 14276- 14287.
[30]	L. Yang, J. Watling, M. Borici, R. C. W. Wilkins, A. Asenov, J. R. Barker and S. Roy, “Simulations of Scaled Sub-100 nm Strained Si/SiGe p-Channel MOSFETs,” Journal of Computational Electronics, Vol. 2, 2004, pp. 363-368.
[31]	L. Yang, J. R. Watling, R. C. W. Wilkins, M. Borici, J. R. Barker, A. Asenov and S. Roy, “Si/SiGe Heterostructure Parameters for Device Simulations,” Semiconductor Science and Technology, Vol. 19, No. 10, 2004, pp. 1174- 1182.
[32]	R. People and J. C. Bean, “Band Alignments of Coherently Strained GexSi1 – x/Si Heterostructures on <001> GeySi1 – y Substrates,” Applied Physics Letters, Vol. 48, 1986, pp. 538-541.
[33]	M. M. Rieger and P. Vogl, “Electronic Band Parameters in Strained Si1 – xGex Alloys on Si1 – yGey Substrates,” Physical Review B, Condensed Matter, Vol. 48, No. 19, pp. 14276-14276, 1993.
[34]	Synopsys, Inc., “Sentaurus Device User Guide,” Version A-2008.09, Synopsys, Inc., Mountain View, 2008.
[35]	J. L. Egley and D. Chidam-barrao, “Strain Effects on Device Characteristics: Implementation in Drift-Diffusion Simulators,” Solid-State Electronics, Vol. 36, No. 12, 1993, pp. 1653-1664.
[36]	N. D. Arora, “MOSFET Models for VLSI Circuit Simulation,” Springer-Verlag, New York, 1993.
[37]	H. C. de Graaff and F. M. Klaassen, “Compact Transistor Modelling for Circuit Design,” Springer-Verlag, New York, 1990.
[38]	J. R. Brews, “A Charge-Sheet Model of the MOSFET,” Solid-State Electronics, Vol. 21, No. 2, 1978, pp. 345- 355.
[39]	R. V. Langevelde and F. M. Klaassen, “An Explicit Surface-Potential-Based MOSFET Model for Circuit Simulation,” Solid-State Electronics, Vol. 44, No. 3, 2000, pp. 409-418.