Design of Low Power and High Speed CMOS Comparator for A/D Converter Application


This paper presents an improved method for design of CMOS comparator based on a preamplifier-latch circuit driven by a clock. Design is intended to be implemented in Sigma-delta Analog-to-Digital Converter (ADC). The main advantage of this design is capable to reduce power dissipation and increase speed of an ADC. The design is simulated in 0.18 μm CMOS Technology with Cadence environment. Proposed design exhibits good accuracy and a low power consumption about 102 μW with operating sampling frequency 125 MHz and 1.8 V supply. Simulation results are reported and compared with earlier work done and improvements are observed in this work.

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S. Yewale and R. Gamad, "Design of Low Power and High Speed CMOS Comparator for A/D Converter Application," Wireless Engineering and Technology, Vol. 3 No. 2, 2012, pp. 90-95. doi: 10.4236/wet.2012.32015.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] B. Razavi, “Deign of Analog CMOS Integrated Circuits,” Tata McGraw-Hill, Delhi, 2002.
[2] R. Wang, K. Li, J. Zhang and B. Nie, “A High Speed High Resolution Latch Comparator For-Pipeline ADC,” IEEE International Workshop on Anti-counterfeiting, Security, Identification, Xiamen, 16-18 April 2007, pp. 28-31.
[3] W. Rong, W. Xiaobo and Y. Xiaolang, “A Dynamic CMOS Comparator with High Precision and Resolution,” IEEE Proceedings of 7th International Conference on Solid-State and Integrated Circuits Technology, 18-21 October 2004, pp. 1567-1570.
[4] J. Wu, “A 100-MHz Pipelined CMOS Comparator,” IEEE Journal of Solid State Circuits, Vol. 23, No. 6, 1988, pp. 1379-1385. doi:10.1109/4.90034
[5] J. M. Kim, “A 6-Bit 1.3 GSample/s A/D Converter in 0.35 μm CMOS,” Doctor Thesis, University of Texas at Dallas, Dallas, 2005.
[6] G. Yongheng, C. Wei, L. Tiejun and W. Zongmin, “A Novel 1GSPS Low Offset Comparator for High Speed ADC,” 5th International Joint Conference on INC, IMC and IDC, IEEE Computer Society, Seoul, 25-27 August 2009, pp. 1251-1254.
[7] D. A. Johns and K. Martin, “Analog Integrated Circuit Design,” John Wiley and Sons, Inc., New York, 1997.
[8] A. Mohan, A. Zayegh, A. Stoiceyski and R. Veljanoyski, “Comparator for High Speed Low Power Ultra Wideband A/D Converter”, International Conference on Communication, Computer and Power (ICCCP), Muscat, 19-21 February 2007, pp. 1-5.
[9] P. R. Gray and R. G. Meyer, “Analysis and Design of Analog Integrated Circuits,” 3rd Edition, John Wiley & Sons, Inc., Hoboken, 1993.
[10] P. E. Allen and D. R. Holberg, “CMOS Analog Circuit Design,” Second Edition, Oxford University, Oxford, 2007.
[11] Y. Degerli, N. Fourches, M. Rouger and P. Lut, “Low Power Autozeroed High-Speed Comparator for the Read- out Chain of a CMOS Monolithic Active Pixel Sensor Based Vertex Detector,” IEEE Transactions on Nuclear Science, Vol. 50, No. 5, 2003, pp. 1-21.
[12] Y. Sun, Y. S. Wang and F. C. Lai, “Low Power High Speed Switched Current Comparator,” IEEE 14th International Conference, Ciechocinek, 21-23 June 2007, pp. 305-308.
[13] M. Panchore and R. S. Gamad, “Low Power and High Speed CMOS Comparator Design Using 0.18 μm Technology,” International Journal of Electronic Engineering Research, Research India Publications, Vol. 2, No. 1, 2010, pp. 71-77.
[14] H. Nyquist, “Certain Topics in Telegraph Transmission Theory,” Transactions of the AIEE, Vol. 47, No. 2, 1928, pp. 617-644.
[15] C. Wulff and T. Ytterdal, “0.8V 1GHz Dynamic Comparator in Digital 90nm CMOS Technology,” IEEE 23rd NORCHIP Conference, 21-22 November 2005, pp. 237- 240.

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