[1]
|
P. Leroux and M. Steyaert, “High-performance 5.2GHz LNA with on-chip inductor to provide ESD protection,” Electronics Letters, Vol. 37, pp. 467–469, March 2001.
|
[2]
|
B. Kleveland, T. J. Maloney, I. Morgan, L. Madden, T. H. Lee, and S. S. Wong, “Distributed ESD protection for high-speed integrated circuits,” IEEE Transactions on Electron Devices, Vol. 21, pp. 390–392, August 2000.
|
[3]
|
S. Hyvonen, S. Joshi, and E. Rosenbaum, “Cancellation technique to provide ESD protection for multi-GHz RF inputs,” Electronic Letters, Vol. 39, No. 3, pp. 284–286, February 2003.
|
[4]
|
A. Chatterjee and T. Polgreen, “A low-voltage triggering SCR for on-chip ESD protection at output and input pads,” IEEE Electron Device Letters, Vol. 12, pp. 21–22, August 1991.
|
[5]
|
E. R. Worley, R. Gupta, B. Jones, R. Kjar, C. Nguyen, and M. Tennyson, “Sub-micron chip ESD protection schemes which avoid avalanching junctions,” in Processing, EOS/ ESD Symposium, pp. 13–20, 1995.
|
[6]
|
H. Feng, G. Chen, R. Zhan, Q. Wu, X. Guan, H. Xie, and A. Z. H. Wang, “A mixed-mode ESD protection circuit simulation-design methodology,” IEEE Journal Soilid- State Circuits, Vol. 38, pp. 995–1006, June 2003.
|
[7]
|
B. Fankhauser and B. Deutschmann, “Using device simulations to optimize ESD protection circuits”, in Processing, IEEE EMC Symposium, pp. 963–968, 2004.
|
[8]
|
ATLAS II Framework, Version 5.10.2.R, Silvaco International, 2005.
|
[9]
|
A. Amerasekera, L. van Roozendaal, J. Bruines, and F. Kuper, “Characterization and modeling of second breakdown in nMOST’s for extraction and ESD-related process and design parameters,” IEEE Transactions on Electron Devices, Vol. 38, pp. 2161–2168, September 1991.
|
[10]
|
C. H. Diaz, S. M. Kang, and C. Duvvury, “Modeling of electrical overstress in integrated circuit,” Kluwer Academic Publishers, 1995.
|
[11]
|
Z. H. Liu, E. Rosenbaum, P. K. Ko, C. Hu, Y. C. Cheng, C. G. Sodini, B. J. Gross, and T. P. Ma, “A comparative study of the effect of dynamic stressing on high-field endurance and stability of reoxidized-nitrided, fluorinated and conventional oxides,” in IEDM Technology Digest, pp. 723–726, 1991.
|
[12]
|
G. Chen, H. Fang, and A. Wang, “A systematic study of ESD protection structures for RF ICs,” in Processing, IEEE Radio Frequency Integrated Circuit Symposium, Vol. 46, pp. 347–350, 2003.
|
[13]
|
J. Y. Choi, “AC modeling of the ggNMOS ESD protection device,” ETRI Journal, Vol. 27, No. 5, pp. 628–634, October 2005.
|