On the Production Testing of Memristor Ratioed Logic (MRL) Gates

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Circuits and Systems

ISSN Print: 2153-1285
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"On the Production Testing of Memristor Ratioed Logic (MRL) Gates"
written by Ahmed Shukry Emara, Ahmed Hassan Madian, Hassanein Hamed Amer, Sherif Hassanein Amer, Mohamed Bakr Abdelhalim,
published by Circuits and Systems, Vol.7 No.10, 2016

has been cited by the following article(s):

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CrossRef

[1]	A Calibrated Memristor Model Implementation for an SR-Latch Based on CMOS-Memristor Technology
	2024 IEEE 15th Latin America …, 2024

[2]	A Testability Enhancement Method for the Memristor Ratioed Logic Circuits
	2020

[3]	Memristive Circuit Design of Five-Person Voter Based on Memristor Ratioed Logic
	2020

[4]	Testing of memristor ratioed logic (MRL) XOR gate
	2016

[1]	A Calibrated Memristor Model Implementation for an SR-Latch Based on CMOS-Memristor Technology 2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS), 2024 DOI:10.1109/LASCAS60203.2024.10506178

[2]	A Calibrated Memristor Model Implementation for an SR-Latch Based on CMOS-Memristor Technology 2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS), 2024 DOI:10.1109/LASCAS60203.2024.10506178

[3]	A Testability Enhancement Method for the Memristor Ratioed Logic Circuits 2020 IEEE 29th Asian Test Symposium (ATS), 2020 DOI:10.1109/ATS49688.2020.9301537

[4]	Testing of memristor ratioed logic (MRL) XOR gate 2016 28th International Conference on Microelectronics (ICM), 2016 DOI:10.1109/ICM.2016.7847939

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