Ultra-Low Power Designing for CMOS Sequential Circuits

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International Journal of Communications, Network and System Sciences

ISSN Print: 1913-3715
ISSN Online: 1913-3723
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"Ultra-Low Power Designing for CMOS Sequential Circuits"
written by Patikineti Sreenivasulu, Srinivasa Rao, Vinaya Babu,
published by International Journal of Communications, Network and System Sciences, Vol.8 No.5, 2015

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[4]	An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates The Scientific World Journal, 2015 DOI:10.1155/2015/621012

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