has been cited by the following article(s):
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[1]
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An Efficient Low-Latency and High Throughput LED Cipher Architecture for IoT Security on a Hardware Platform
SN Computer Science,
2024
DOI:10.1007/s42979-024-03275-5
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[2]
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High Throughput PRESENT Cipher Hardware Architecture for the Medical IoT Applications
Cryptography,
2023
DOI:10.3390/cryptography7010006
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[3]
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10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform
Electronics,
2020
DOI:10.3390/electronics9101665
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[4]
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A Novel Hardware-Efficient Central Pattern Generator Model Based on Asynchronous Cellular Automaton Dynamics for Controlling Hexapod Robot
IEEE Access,
2020
DOI:10.1109/ACCESS.2020.3012706
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[5]
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10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform
Electronics,
2020
DOI:10.3390/electronics9101665
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[6]
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A Dynamic Reconfigurable Design of Multiple Cryptographic Algorithms Based on FPGA
2018 IEEE International Conference on Smart Internet of Things (SmartIoT),
2018
DOI:10.1109/SmartIoT.2018.00-17
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[7]
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First steps towards designing a compact language for the description of logic circuits
2016 International Conference on Communications (COMM),
2016
DOI:10.1109/ICComm.2016.7528313
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