Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

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ISSN Print: 2153-1285
ISSN Online: 2153-1293
www.scirp.org/journal/cs
E-mail: cs@scirp.org

"Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits"
written by Omnia S. Ahmed, Mohamed F. Abu-Elyazeed, Mohamed B. Abdelhalim, Hassanein H. Amer, Ahmed H. Madian,
published by Circuits and Systems, Vol.4 No.3, 2013

has been cited by the following article(s):

[1]	DEVELOPMENT OF LOW POWER VITERBI DECODER ON COMPLEX PROGRAMMABLE LOGIC DEVICE PLATFORM
	2018

[2]	Data structures for SIMD logic simulation
	2016

[3]	Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model
	Journal of Advanced Research, 2015

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