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[1]
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A Novel Approach for Dynamic Power Reduction in SRAM Cache Memory Bit-Cell at Deep Sub-Micron CMOS Technology
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… on Communication & …,
2023 |
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[2]
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A study of emerging semi-conductor devices for memory applications
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2021 |
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[3]
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NOVEL LOW POWER HALF-SUBTRACTOR USING AVL WITH SLEEP TRANSISTOR TECHNIQUE BASED ON 0.18 µM CMOS TECHNOLOGY
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International Journal of Modern Trends in Engineering Science,
2018 |
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[4]
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Implementation of Static RAM with Sleep Transistor to Leakage Power Reduction
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International Journal of Contemporary Technology and Management,
2017 |
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[5]
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Low Leakage Asynchronous PP based Single Ended 8T SRAM bit-cell at 45nm CMOS Technology
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2016 |
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[6]
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模拟集成电路设计实训.
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Research & Exploration in Laboratory,
2015 |
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Design and Analysis of a Novel Ultra-Low Power SRAM Bit-Cell at 45nm CMOS Technology for Bio-Medical Implants
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International Journal of Computer Applications,
2015 |
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[8]
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A Roadmap on the Low Power Static Random Access Memory Design Topologies
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J Yadav, T Goswami, P Bhatnagar, S Birla, NK Shukla - ijser.org,
2014 |
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[9]
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Evaluation of microscopy as a field laboratory test for diagnosis of Johne's disease in farm animals.
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Intas Polivet,
2014 |
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[10]
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Design a Low Power Half-Subtractor Using AVL Technique Based on 65nm CMOS Technology
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International Journal of Advanced Research in Computer Engineering & Technology (IJARCET),
2013 |
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[11]
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Analysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology
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International Journal of Computer Applications? ,
2013 |
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[12]
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Effect of Supply Voltage on Ability and Stability in IP3 SRAM Bit-Cell at 45nm CMOS Technology using N-Curve
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International Journal of Computer Applications,
2013 |
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[13]
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Gate leakage current reduction in IP3 SRAM cells at 45 nm CMOS technology for multimedia applications
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Journal of Semiconductors,
2012 |
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[14]
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Analysis of Subthreshold Leakage Current in IP 3 SRAM Bit-Cell under Temperature Variations in Deep-Submicrometer CMOS Technology
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International Journal of Computer Applications,
2012 |
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[15]
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Analysis of Gate Leakage Current in IP3 SRAM Bit-Cell under Temperature Variations in DSM Technology
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parameters,
2012 |
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[16]
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Implementation of high performance and low leakage half subtractor circuit using AVL technique
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Information and Communication Technologies (WICT), 2012 World Congress on. IEEE, 2012.,
2012 |
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[17]
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An Analysis of Power and Stability in 6T, NC, Asymmetric, PP, and P3SRAM Bit-Cells Topologies in 45nm CMOS Technology
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International Journal of Computer Applications,
2012 |
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[18]
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Analysis and Simulation of Subthreshold Leakage Current Reduction in IP3 SRAM Bit-Cell at 45 nm CMOS Technology for Multimedia Applications
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M Pattanaik, NK Shukla, RK Singh - ijcte.org,
2011 |
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