has been cited by the following article(s):
[1]
|
Area and delay efficient RNS-based FIR filter design using fast multipliers
Measurement: Sensors,
2024
DOI:10.1016/j.measen.2023.101014
|
|
|
[2]
|
Design and implementation of 8-bit wallace multiplier with reduced complexity using Ripple carry adder in comparison with sklansky adder
FIFTH INTERNATIONAL CONFERENCE ON APPLIED SCIENCES: ICAS2023,
2024
DOI:10.1063/5.0203735
|
|
|
[3]
|
Exploring Temperature, Power, and Hardware Utilization in Half Adder Implementation on FPGA Platforms
2024 2nd International Conference on Sustainable Computing and Smart Systems (ICSCSS),
2024
DOI:10.1109/ICSCSS60660.2024.10625065
|
|
|
[4]
|
Design and implementation of 8 - bit multiplier using carry adder by comparing with carry look ahead
INTERNATIONAL CONFERENCE ON SCIENCE, ENGINEERING, AND TECHNOLOGY 2022: Conference Proceedings,
2023
DOI:10.1063/5.0173382
|
|
|
[5]
|
Advanced Computing and Intelligent Engineering
Advances in Intelligent Systems and Computing,
2020
DOI:10.1007/978-981-15-1483-8_13
|
|
|
[6]
|
Power and Justice
China Academic Library,
2019
DOI:10.1007/978-981-13-5802-9_67
|
|
|