Implementation of <i>N</i>-Bit Binary Multiplication Using <i>N</i> - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method

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ISSN Print: 2153-1285
ISSN Online: 2153-1293
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"Implementation of N-Bit Binary Multiplication Using N - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method"
written by M. Nisha Angeline, S. Valarmathy,
published by Circuits and Systems, Vol.7 No.9, 2016

has been cited by the following article(s):

[1]	Comparative analysis of Yavadunam Tavadunikrtya Varganca Yojayet Vedic multiplier for embedded DNN
	Sādhanā, 2022

[2]	The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising
	2021

[3]	Design and investigation of low-complexity Anurupyena Vedic multiplier for machine learning applications
	2020

[4]	Low power 4× 4 bit multiplier design using dadda algorithm and optimized full adder
	2018

[5]	Design of implementation of efficient 4× 4 Bit Multiplier using Dadda Algorithm and Optimized Full Adder
	International Journal of Research, 2018

[6]	FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics
	2018

[7]	Comparison of multiplication algorithms based on FPGA
	2018

[1]	Comparative analysis of Yavadunam Tavadunikrtya Varganca Yojayet Vedic multiplier for embedded DNN Sādhanā, 2022 DOI:10.1007/s12046-022-01843-0

[2]	Advances in Multidisciplinary Medical Technologies ─ Engineering, Modeling and Findings 2021 DOI:10.1007/978-3-030-57552-6_12

[3]	Design and investigation of low-complexity Anurupyena Vedic multiplier for machine learning applications Sādhanā, 2020 DOI:10.1007/s12046-020-01500-4

[4]	Comparison of Multiplication Algorithms Based on FPGA 2018 2nd Borneo International Conference on Applied Mathematics and Engineering (BICAME), 2018 DOI:10.1109/BICAME45512.2018.1570505372

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