Area and Speed Efficient Implementation of Symmetric FIR Digital Filter through Reduced Parallel LUT Decomposed DA Approach

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ISSN Print: 2153-1285
ISSN Online: 2153-1293
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"Area and Speed Efficient Implementation of Symmetric FIR Digital Filter through Reduced Parallel LUT Decomposed DA Approach"
written by S. C. Prasanna, S. P. Joy Vasantha Rani,
published by Circuits and Systems, Vol.7 No.8, 2016

has been cited by the following article(s):

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[1]	Decimator systolic arrays design space exploration for multirate signal processing applications IET Circuits, Devices & Systems, 2019 DOI:10.1049/iet-cds.2019.0077