has been cited by the following article(s):
[1]
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Design and implementation of power and area optimized AES architecture on FPGA for IoT application
Circuit World,
2020
DOI:10.1108/CW-04-2019-0039
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[2]
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10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform
Electronics,
2020
DOI:10.3390/electronics9101665
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