Design of Efficient Router with Low Power and Low Latency for Network on Chip

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ISSN Print: 2153-1285
ISSN Online: 2153-1293
www.scirp.org/journal/cs
E-mail: cs@scirp.org

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"Design of Efficient Router with Low Power and Low Latency for Network on Chip"
written by M. Deivakani, D. Shanthi,
published by Circuits and Systems, Vol.7 No.4, 2016

has been cited by the following article(s):

[1]	ANALYSIS OF IMPROVED EZ-PASS ROUTER DESIGN AND ITS FPGA IMPLEMENTATION
	JOURNAL OF HARBIN …, 2021

[2]	Performance Analysis of Clustering-Based Topology Generation and disable nodes for NoC
	2018

[3]	A genetic algorithm approach for global routing of VLSI circuits
	2018

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