A 1-GHz, 7-mW, 8-Bit Subranging ADC without Resistor Ladder Using Built-In Threshold Calibration

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ISSN Print: 2153-1285
ISSN Online: 2153-1293
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"A 1-GHz, 7-mW, 8-Bit Subranging ADC without Resistor Ladder Using Built-In Threshold Calibration"
written by Kenichi Ohhata, Wataru Yoshimura, Daiki Tabira, Futoshi Shimozono, Masataro Iwamoto,
published by Circuits and Systems, Vol.5 No.4, 2014

has been cited by the following article(s):

[1]	Analog to digital converter with digital reference voltage signal
	2017

[2]	Modeling of Ideal and Error Characteristics of a Multi–Stage, Time Interleaved Sub–Ranging Analog to Digital Converter using MATLAB.
	2016

[3]	High-Speed, Low-Power Subranging ADCs
	2015

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[1]	High-speed, low-power subranging ADCs 2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2015 DOI:10.1109/RFIT.2015.7377924