Design of Low Power Comparator Using DG Gate

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Circuits and Systems

ISSN Print: 2153-1285
ISSN Online: 2153-1293
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"Design of Low Power Comparator Using DG Gate"
written by Bahram Dehghan, Abdolreza Roozbeh, Jafar Zare,
published by Circuits and Systems, Vol.5 No.1, 2014

has been cited by the following article(s):

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CrossRef

[1]	Novel Reversible Comparator Design in Quantum Dot-Cellular Automata with Power Dissipation Analysis
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[2]	Design of a new BUS for low power reversible computation
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[5]	Performance analysis of 1-bit full adder using different design techniques
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[6]	A Novel Reversible EX-NOR SV Gate and Its Application
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[7]	Design & Optimization of Reversible Logic Based ALU Using ACO
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[8]	Design & Optimization of Reversible Logic Based ALU Using ACO.
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[9]	Implementation and Analysis of Reversible logic Based Arithmetic Logic Unit
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[10]	Design Analysis of 1-bit Comparator using 45nm Technology
	International Journal of Engineering Trends and Technology (IJETT) , 2016

[11]	JSM gate—A new proposition in spin based reversible logic circuitry
	2016

[12]	Optimized design and performance analysis of novel comparator and full adder in nanoscale
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[13]	Reversible binary subtractor design using quantum dot-cellular automata
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[15]	Reversible Comparator Design Using Quantum Dot-Cellular Automata
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[16]	Reversible Comparator Circuit Using a New Reversible Gate
	Proceedings of the Sixth International Conference on Computer and Communication Technology 2015, 2015

[17]	Evolution of structure of some binary group based n bit comparator, n-to-2n decoder by reversible technique
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[18]	Quantum cost realization of new reversible gates with transformation based synthesis technique
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[19]	EVOLUTION OF STRUCTURE OF SOME BINARY GROUP-BASED NBit COMPARATOR, NTo-2 N DECODER BY REVERSIBLE TECHNIQUE
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[20]	Post synthesis optimization of reversible logic functions with extended template matching
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[1]	Novel Reversible Comparator Design in Quantum Dot-Cellular Automata with Power Dissipation Analysis Applied Sciences, 2022 DOI:10.3390/app12157846

[2]	Design of a new BUS for low power reversible computation Computers & Electrical Engineering, 2021 DOI:10.1016/j.compeleceng.2020.106938

[3]	Computer Communication, Networking and Internet Security Lecture Notes in Networks and Systems, 2017 DOI:10.1007/978-981-10-3226-4_10

[4]	Reversible binary subtractor design using quantum dot-cellular automata Frontiers of Information Technology & Electronic Engineering, 2017 DOI:10.1631/FITEE.1600999

[5]	Reversible Comparator Design Using Quantum Dot-Cellular Automata IETE Journal of Research, 2016 DOI:10.1080/03772063.2015.1088407

[6]	Optimized design and performance analysis of novel comparator and full adder in nanoscale Cogent Engineering, 2016 DOI:10.1080/23311916.2016.1237864

[7]	JSM gate — A new proposition in spin based reversible logic circuitry 2016 IEEE 7th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON), 2016 DOI:10.1109/UEMCON.2016.7777928

[8]	Quantum cost realization of new reversible gates with transformation based synthesis technique 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), 2015 DOI:10.1109/VLSI-SATA.2015.7050491

[9]	Post synthesis optimization of reversible logic functions with extended template matching International Conference on Circuits, Communication, Control and Computing, 2014 DOI:10.1109/CIMCA.2014.7057825

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