An Improved SOI CMOS Technology Based Circuit Technique for Effective Reduction of Standby Subthreshold Leakage

Circuits and Systems

ISSN Print: 2153-1285
ISSN Online: 2153-1293
www.scirp.org/journal/cs
E-mail: cs@scirp.org

Citations h5-index & Ranking*

Journals Menu

"An Improved SOI CMOS Technology Based Circuit Technique for Effective Reduction of Standby Subthreshold Leakage"
written by Manish Kumar, Md. Anwar Hussain, Sajal K. Paul,
published by Circuits and Systems, Vol.4 No.6, 2013

has been cited by the following article(s):

Google Scholar
CrossRef

[1]	Comparative Analysis & Study of Various Leakage Reduction Techniques for Short Channel Devices in Junctionless Transistors: A Review and Perspective
	2021

[2]	The Significance on Structural Modulation of Buffer and Gate Insulator for ALD Based InGaZnO TFT Applications
	… on Electron Devices, 2021

[3]	Performance Assessment of Sub Threshold Leakage Current Reduction and Power Dissipation in MOSFET for Si, SiGe and GaN Using COMSOL MULTIPHYSICS
	2021 Emerging Trends in Industry 4.0 …, 2021

[4]	Improved performance and stability of In-Sn-Zn-O thin film transistor by introducing a meso-crystalline ZrO2 high-k gate insulator
	2019

[5]	New High Performance Low Power Carry Look Ahead Adder With Reduce Ground Bounce Noise Using MTCMOS Technique
	2017

[6]	Design and Analysis of Low power Carry Look ahead Adder using forward body biased Stacking Power Gating Technique.
	2017

[7]	Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies
	2017

[8]	Nodal thermal analysis for multi-VT SOFFET based subthreshold circuits
	2017

[9]	Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging …
	2017

[10]	Delay and Energy Efficiency Analysis of a 1-bit CMOS Full Adder
	2016

[11]	Lipid layers as ultra-thin dielectric for highly sensitive ions field effect transistor sensors
	Thesis, 2016

[12]	Power-gating schemes for super-threshold FinFET CML circuits
	2016

[13]	Low Power High Speed Multiplier Design based on MTCMOS Technique
	2016

[14]	Delay and Energy Efficiency Analysis of a 1-bit CMOS Full Adder.
	Journal of Active & Passive Electronic Devices, 2016

[15]	A New Power Gating Circuit Design Approach using Double-Gate FDSOI
	2016

[16]	Design of Ultra-Low Power PMOS and NMOS for Nano Scale VLSI Circuits
	Circuits and Systems, 2015

[1]	Comparative Analysis & Study of Various Leakage Reduction Techniques for Short Channel Devices in Junctionless Transistors: A Review and Perspective Silicon, 2022 DOI:10.1007/s12633-021-01181-6

[2]	The Significance on Structural Modulation of Buffer and Gate Insulator for ALD Based InGaZnO TFT Applications IEEE Transactions on Electron Devices, 2021 DOI:10.1109/TED.2021.3117749

[3]	Performance Assessment of Sub Threshold Leakage Current Reduction and Power Dissipation in MOSFET for Si, SiGe and GaN Using COMSOL MULTIPHYSICS 2021 Emerging Trends in Industry 4.0 (ETI 4.0), 2021 DOI:10.1109/ETI4.051663.2021.9619434

[4]	Improved performance and stability of In-Sn-Zn-O thin film transistor by introducing a meso-crystalline ZrO2 high-k gate insulator Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, 2019 DOI:10.1116/1.5079834

[5]	Improved performance and stability of In-Sn-Zn-O thin film transistor by introducing a meso-crystalline ZrO2 high-k gate insulator Journal of Vacuum Science & Technology A, 2019 DOI:10.1116/1.5079834

[6]	A New Power Gating Circuit Design Approach Using Double-Gate FDSOI IEEE Transactions on Circuits and Systems II: Express Briefs, 2018 DOI:10.1109/TCSII.2016.2618768

[7]	Nodal thermal analysis for multi-VT SOFFET based subthreshold circuits 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017 DOI:10.1109/ISCAS.2017.8050826

[8]	Design of Ultra-Low Power PMOS and NMOS for Nano Scale VLSI Circuits Circuits and Systems, 2015 DOI:10.4236/cs.2015.63007

	+1 323-425-8868
	customer@scirp.org
	+86 18163351462(WhatsApp)
	1655362766

	Paper Publishing WeChat

	+1 323-425-8868
	customer@scirp.org
	+86 18163351462(WhatsApp)
	1655362766

	Paper Publishing WeChat

Circuits and Systems

Circuits and Systems

Journals Menu

Home

About SCIRP

Service

Policies